corundum/corundum issues and pull requests

#96 - fix partial initialisation of memory

Pull Request - State: closed - Opened by Basseuph over 2 years ago

#95 - how to make fpga.mcs

Issue - State: closed - Opened by wyz1031 over 2 years ago - 17 comments

#94 - Mle/mlab fix

Pull Request - State: open - Opened by Simon-Lever over 2 years ago - 1 comment

#93 - tx_req_mux tag width mismatch

Issue - State: open - Opened by andreasbraun90 over 2 years ago

#92 - Support 10 Gbps on 100 Gbps design

Issue - State: closed - Opened by mclayton1000 over 2 years ago - 12 comments

#91 - IPv6 support

Issue - State: open - Opened by kaoruzhu1 over 2 years ago - 1 comment

#90 - Simulation throws IndexError in TxRing-free_desc function for Tx packet count > 1024

Issue - State: closed - Opened by andreasbraun90 over 2 years ago - 5 comments

#89 - Error changing RX/TX_QUEUE_INDEX_WIDTH in Simulation

Issue - State: closed - Opened by andreasbraun90 over 2 years ago - 6 comments

#88 - Support of 1Gb Ethernet and cheaper FPGA families

Issue - State: closed - Opened by ohault over 2 years ago - 7 comments

#87 - modules/mqnic: Custom TX queue selection

Pull Request - State: open - Opened by joft-mle over 2 years ago - 5 comments

#86 - cocotb sim error with cadence simulator (with walk-around)

Issue - State: open - Opened by kaoruzhu1 over 2 years ago - 3 comments

#85 - BUG: unable to handle page fault for address, during mqnic_prepare_rx_desc/mqnic_refill_rx_buffers

Issue - State: closed - Opened by articice over 2 years ago - 2 comments

#84 - TLP package

Issue - State: open - Opened by beer-belly over 2 years ago - 8 comments

#83 - various small changes

Pull Request - State: closed - Opened by joft-mle almost 3 years ago

#82 - Enabling app will break axis_async_fifo.tcl contraints

Issue - State: closed - Opened by likewise almost 3 years ago - 6 comments

#81 - add .gitignore files in fpga build folders

Pull Request - State: closed - Opened by Basseuph almost 3 years ago - 4 comments

#80 - support more than 4k queues (workaround quartus loop iteration limit)

Pull Request - State: closed - Opened by Basseuph almost 3 years ago - 6 comments

#79 - Device needs to be reset

Issue - State: closed - Opened by miracleq5 almost 3 years ago - 1 comment

#78 - Mle/tb/tox versions

Pull Request - State: closed - Opened by sessl3r almost 3 years ago - 3 comments

#77 - Tx Descriptor length feedback

Issue - State: open - Opened by andreasbraun90 almost 3 years ago

#76 - errors by using pytest when test corundum

Issue - State: open - Opened by su-33 almost 3 years ago - 10 comments

#75 - A switch fabric inside Corundum

Issue - State: open - Opened by Winters123 almost 3 years ago - 7 comments

#74 - How could I make Alveo U50 detective by Vivado HARDWARE MANAGER？

Issue - State: open - Opened by IskandarZhang almost 3 years ago - 9 comments

#73 - Wrong BAR registers

Issue - State: closed - Opened by minlno almost 3 years ago - 8 comments

#72 - use default_nettype none in corundum verilog files

Pull Request - State: closed - Opened by sessl3r almost 3 years ago - 3 comments

#70 - `AU200/fpga_100g` cocotb test is broken

Issue - State: closed - Opened by lomotos10 about 3 years ago - 2 comments

#69 - Does queue_manager ignore the back pressure on s_axil_bready?

Issue - State: open - Opened by jeehoonkang about 3 years ago - 9 comments

#68 - Missing ethtool definitions in mqnic module for new kernel 5.11

Issue - State: closed - Opened by nightseas about 3 years ago - 2 comments

#67 - Driver Error

Issue - State: open - Opened by BearRiding about 3 years ago - 10 comments

#66 - jnbhgrf'、【。；，立刻就你不感觉天【pyrtzgfhj

Issue - State: closed - Opened by isuckatdrifting about 3 years ago - 2 comments

#65 - jnbhgrf'、【。；，立刻就你不感觉天

Issue - State: closed - Opened by isuckatdrifting about 3 years ago - 1 comment

#64 - Is it possible to port the project to 1Gbe?

Issue - State: open - Opened by Quenii about 3 years ago - 3 comments

#62 - module verifcation failed:signature and/or required key missing ---tainting

Issue - State: open - Opened by wengmomo about 3 years ago - 1 comment

#61 - How to use verilator in the simulation?

Issue - State: open - Opened by kevinyuan about 3 years ago - 1 comment

#60 - Add cmac_pad testbench

Pull Request - State: closed - Opened by minseongg about 3 years ago - 7 comments

#59 - port to bittware xup-p3r board for 100g

Pull Request - State: closed - Opened by giraypultar over 3 years ago - 1 comment

#58 - Synth Error

Issue - State: closed - Opened by bizhaan47 over 3 years ago - 11 comments

#57 - Zynq support

Issue - State: closed - Opened by ollie-etl over 3 years ago - 29 comments

#55 - [General question] RDMA support

Issue - State: closed - Opened by wtao0221 over 3 years ago - 1 comment

#54 - Implement ethtool get_eeprom and set_eeprom APIs

Issue - State: open - Opened by alexforencich over 3 years ago - 3 comments
Labels: enhancement

#53 - mqnic module compile error

Issue - State: open - Opened by kimanha over 3 years ago - 12 comments

#52 - Understanding the queue management and DMA modules in Corundum

Issue - State: open - Opened by Winters123 over 3 years ago - 2 comments

#51 - Is there any way to deliver large size packet to FPGA without DPDK?

Issue - State: open - Opened by ParkGyuhwan over 3 years ago - 5 comments

#50 - Add support for adm-pcie-8v3

Issue - State: open - Opened by Applepi over 3 years ago - 2 comments

#49 - support SR-IOV？

Issue - State: open - Opened by wangshuaizs over 3 years ago - 1 comment

#48 - Interfacing CMAC to PCIe x8

Issue - State: closed - Opened by nightseas over 3 years ago - 6 comments

#47 - question about iperf performance

Issue - State: open - Opened by wangshuaizs over 3 years ago - 39 comments

#46 - Test Issue about Constant User Function

Issue - State: open - Opened by happyPisces over 3 years ago - 8 comments

#45 - Make a loopback for performance test

Issue - State: closed - Opened by Winters123 over 3 years ago - 1 comment

#44 - U200 cannot receive packets

Issue - State: open - Opened by xiuwen8686 over 3 years ago - 4 comments

#43 - mqnic_i2c: Fix device_attach() error handling

Pull Request - State: closed - Opened by penberg over 3 years ago - 1 comment

#42 - A few questions about tx_scheduler_rr

Issue - State: open - Opened by charlottewang0801 over 3 years ago

#39 - Support MSI-X

Issue - State: open - Opened by alexforencich almost 4 years ago - 2 comments
Labels: enhancement

#38 - U200 packet receiving performance test

Issue - State: open - Opened by beer-belly almost 4 years ago - 3 comments
Labels: question

#37 - Is the Xilinx UniSim library under Apache 2.0 license useful to you?

Issue - State: closed - Opened by mithro almost 4 years ago - 2 comments

#36 - Not working on Alveo U50DD(Alveo U50-ES3)

Issue - State: closed - Opened by Perlmint almost 4 years ago - 3 comments

#35 - cheaper fpgas

Issue - State: open - Opened by aep almost 4 years ago - 18 comments

#34 - timing issue on AU250

Issue - State: open - Opened by Winters123 almost 4 years ago - 10 comments

#33 - Optimize iperf Performance of External Loopback in Dual-port Design

Issue - State: closed - Opened by nightseas almost 4 years ago - 8 comments
Labels: question

#31 - Migration to customized FPGA board

Issue - State: open - Opened by xtfan almost 4 years ago - 5 comments

#30 - Is there anything I need to modify when using U250/fpga_100g?

Issue - State: closed - Opened by ParkGyuhwan almost 4 years ago - 4 comments

#29 - Is it possible to support bump-in-wire?

Issue - State: open - Opened by YangWang92 almost 4 years ago - 7 comments

#28 - Can you share your Vivado version?

Issue - State: closed - Opened by YangWang92 almost 4 years ago - 3 comments

#27 - simulation based on python

Issue - State: closed - Opened by beer-belly almost 4 years ago

#24 - Cannot connect to switch

Issue - State: closed - Opened by Gaojiaqi almost 4 years ago - 10 comments

#23 - eth_mac_10g_fifo.v minor bug

Issue - State: closed - Opened by adi8v almost 4 years ago - 4 comments
Labels: bug

#22 - PCIe CORE Parameter AXIS_DATAWIDTH = 64 breaks the design.

Issue - State: open - Opened by kaoruzhu1 almost 4 years ago - 3 comments
Labels: enhancement

#21 - How to check whether HW is working correctly?

Issue - State: open - Opened by wtao0221 almost 4 years ago - 21 comments
Labels: question

#20 - fix typo in test_fpga_core.py

Issue - State: closed - Opened by kaoruzhu1 almost 4 years ago - 2 comments
Labels: bug

#19 - PTP mapping of timestamp and eth message

Issue - State: closed - Opened by RenGraef almost 4 years ago - 5 comments
Labels: question

#18 - build VCU118 with vivado 2018.3

Issue - State: closed - Opened by Winters123 almost 4 years ago - 2 comments
Labels: question

#17 - make impl failed at u280 fpga 100g project

Issue - State: closed - Opened by csunclechen almost 4 years ago - 9 comments
Labels: question

#16 - Add some file extensions to gitignore

Pull Request - State: closed - Opened by lastweek almost 4 years ago

#15 - specify xci generation output directory?

Issue - State: open - Opened by TripRichert about 4 years ago - 2 comments

#14 - Support For Intel FPGA?

Issue - State: open - Opened by piotrraczynski about 4 years ago - 9 comments
Labels: enhancement