clash-lang/clash-compiler issues and pull requests

#2660 - `vioProbe` does not handle `XException` values gracefully

Issue - State: open - Opened by martijnbastiaan 9 months ago
Labels: bug, clash-cores

#2658 - cabal: Make workaround-ghc-mmap-crash a noop on non-x86_64 (copy #2657)

Pull Request - State: closed - Opened by mergify[bot] 10 months ago - 2 comments

#2655 - Set names for ILAs and VIOs by default

Issue - State: open - Opened by kleinreact 10 months ago - 16 comments
Labels: enhancement, discussion, clash-cores

#2644 - SPI core mode 0 is racy

Issue - State: open - Opened by bgamari 10 months ago - 3 comments
Labels: clash-cores

#2640 - Haddock: Fix very confusing formatting errors (copy #2622)

Pull Request - State: closed - Opened by mergify[bot] 10 months ago - 3 comments
Labels: conflicts

#2635 - SPI: Generalize to multi-lane MOSI/MISO

Pull Request - State: open - Opened by bgamari 10 months ago - 22 comments
Labels: clash-cores

#2628 - HDL generation failure with clash 1.8.1 ghc 9.4.7

Issue - State: closed - Opened by pbreuer 11 months ago - 14 comments

#2617 - Sigma Delta ADC

Pull Request - State: open - Opened by FloriaanB 12 months ago - 1 comment
Labels: clash-cores

#2615 - Amend `RELEASING.md`

Pull Request - State: closed - Opened by DigitalBrains1 12 months ago - 2 comments

#2584 - Move i2c to clash cores

Pull Request - State: open - Opened by lmbollen about 1 year ago
Labels: clash-cores

#2576 - Enable ghc mmap crash workaround for every ghc compiled binary (copy #2572)

Pull Request - State: closed - Opened by mergify[bot] about 1 year ago
Labels: conflicts

#2498 - VIO probes always output `undefined`, making them hard to use in simulation

Issue - State: open - Opened by martijnbastiaan over 1 year ago - 3 comments
Labels: enhancement, clash-cores

#2492 - Generate correct SDC for Vivado

Pull Request - State: closed - Opened by NadiaYvette over 1 year ago - 8 comments

#2376 - Clash error call: `zipEqual: left list is longer` when using custom type proof

Issue - State: open - Opened by martijnbastiaan almost 2 years ago - 11 comments
Labels: enhancement

#2258 - Don't terminate Verilog simulator on error in assertion functions

Pull Request - State: closed - Opened by acairncross over 2 years ago - 10 comments

#2231 - (Optionally) Sequential Black Boxes

Pull Request - State: closed - Opened by alex-mckenna over 2 years ago - 2 comments

#2181 - Render sequential processes in VHDL

Pull Request - State: closed - Opened by alex-mckenna over 2 years ago - 4 comments

#2164 - Preserve non-recursive let in normalization

Pull Request - State: closed - Opened by alex-mckenna over 2 years ago - 2 comments

#1928 - Keep casts of the form `x ~ Integer`

Pull Request - State: closed - Opened by christiaanb about 3 years ago - 1 comment

#1725 - Partial Evaluator II

Pull Request - State: closed - Opened by alex-mckenna over 3 years ago - 1 comment

#1526 - Add a "high-speed" version of `autoReg`

Pull Request - State: closed - Opened by christiaanb about 4 years ago - 2 comments

#1168 - autoDelay: autoReg without the reset

Pull Request - State: closed - Opened by christiaanb over 4 years ago

#1064 - Keep all casts, and cast `Signal a ~ a` where appropriate

Pull Request - State: open - Opened by christiaanb almost 5 years ago - 1 comment

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