Ecosyste.ms: Issues
An open API service for providing issue and pull request metadata for open source projects.
GitHub / circuitgraph/circuitgraph issues and pull requests
#37 - Added basic support of multi-bit ports for gate-level netlists
Pull Request -
State: open - Opened by tamood about 1 year ago
#36 - Error while creating a circuit through file
Issue -
State: open - Opened by jenila19 over 1 year ago
#35 - Update to 0.2.1
Pull Request -
State: closed - Opened by rbnprdy over 1 year ago
#34 - fixed import from pysat
Pull Request -
State: open - Opened by gsburmaster almost 2 years ago
#33 - Why to limit the fanout of bb_output?
Issue -
State: closed - Opened by Flians over 2 years ago
- 2 comments
#32 - unexpected output from visualize utility when circuit contains blackbox
Issue -
State: closed - Opened by erblum almost 3 years ago
- 2 comments
#31 - Clean up imports
Issue -
State: closed - Opened by rbnprdy over 3 years ago
Labels: enhancement
#30 - Nodes from blackboxes are not presented correctly.
Issue -
State: open - Opened by zyk101177 over 3 years ago
#29 - Add ability to parse busses
Issue -
State: open - Opened by rbnprdy over 3 years ago
- 1 comment
Labels: enhancement
#28 - Clean up netlists
Issue -
State: open - Opened by rbnprdy over 3 years ago
#27 - Add parsing for "x" valued nodes.
Issue -
State: open - Opened by rbnprdy over 3 years ago
#26 - from_file(path="/netlists/lut_1.v", name="LUT_WINPUT1") fails on lexer
Issue -
State: open - Opened by roy-pstr almost 4 years ago
- 1 comment
#25 - todo
Issue -
State: open - Opened by jpsety almost 4 years ago
#24 - Add "Acknowledgements" section to README.
Pull Request -
State: closed - Opened by ncasti almost 4 years ago
#23 - Update paper.bib
Pull Request -
State: closed - Opened by danielskatz about 4 years ago
#22 - updates to paper & bib
Pull Request -
State: closed - Opened by danielskatz about 4 years ago
#21 - pickle interface
Issue -
State: closed - Opened by jpsety about 4 years ago
- 1 comment
#20 - Interfaces
Issue -
State: open - Opened by prw99r over 4 years ago
- 4 comments
#19 - Synthesis Coverage
Issue -
State: open - Opened by prw99r over 4 years ago
- 4 comments
#18 - Statement of Need Too Narrow and ill defined
Issue -
State: closed - Opened by prw99r over 4 years ago
- 5 comments
#17 - Statement of Need
Issue -
State: closed - Opened by prw99r over 4 years ago
- 1 comment
#16 - synth
Issue -
State: closed - Opened by jpsety over 4 years ago
#15 - subgraph
Issue -
State: closed - Opened by jpsety over 4 years ago
#14 - sat check if node exists
Issue -
State: closed - Opened by jpsety over 4 years ago
- 1 comment
#13 - Add graph visualization/plotting
Issue -
State: closed - Opened by jpsety over 4 years ago
#12 - speed up with caching
Issue -
State: open - Opened by jpsety over 4 years ago
#10 - Unittest
Pull Request -
State: closed - Opened by jpsety over 4 years ago
#9 - Pyverilog
Pull Request -
State: closed - Opened by rbnprdy over 4 years ago
#8 - circuit linter
Issue -
State: closed - Opened by jpsety over 4 years ago
#7 - Add parsing ternary operators
Issue -
State: closed - Opened by rbnprdy over 4 years ago
- 1 comment
Labels: enhancement
#6 - Add parsing constants to assign statements
Issue -
State: closed - Opened by rbnprdy over 4 years ago
- 2 comments
Labels: enhancement
#5 - Output conversion
Pull Request -
State: closed - Opened by jpsety over 4 years ago
#4 - add bench parsing
Issue -
State: closed - Opened by jpsety over 4 years ago
- 2 comments
#3 - add fanin to constants
Issue -
State: closed - Opened by jpsety over 4 years ago
Labels: enhancement
#2 - Add ability to parse concatenation syntax
Issue -
State: open - Opened by rbnprdy over 4 years ago
Labels: enhancement
#1 - Formatting
Pull Request -
State: closed - Opened by rbnprdy over 4 years ago