Ecosyste.ms: Issues

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GitHub / chipsalliance/veerwolf issues and pull requests

#76 - can not access ICCM/DCCM memory with dmi_wrapper module

Issue - State: closed - Opened by alphijiang 2 months ago - 1 comment

#75 - Adding Wolf Pack to VeeRwolves branch

Pull Request - State: closed - Opened by gsinside 3 months ago - 1 comment

#74 - Fix bootrom

Pull Request - State: closed - Opened by MikaelStrom 3 months ago - 1 comment

#73 - Add target for an Intel Agilex 5 premium devkit.

Pull Request - State: closed - Opened by Gostas 3 months ago - 1 comment

#72 - Updating wb_intercon

Issue - State: closed - Opened by gsinside 4 months ago - 2 comments

#71 - Added support for Digilent Nexys Video.

Pull Request - State: closed - Opened by MikaelStrom 6 months ago - 1 comment

#70 - Fix comment for register addresses in syscon

Pull Request - State: closed - Opened by cdhmanning 9 months ago - 1 comment

#69 - Error in Build of Predefined examples of Zephyr

Issue - State: open - Opened by minecraftdixit 10 months ago - 1 comment

#67 - Assertion error when running fusesoc simulation

Issue - State: open - Opened by MoonisAmir10 about 1 year ago - 6 comments

#65 - Update Readme file with missing instructions

Pull Request - State: closed - Opened by SriQamcom over 1 year ago - 1 comment

#64 - Changes to work with zephyr 2.7.4.

Pull Request - State: closed - Opened by anders-ahlberg over 1 year ago - 1 comment

#63 - Error when building Zephyr example

Issue - State: open - Opened by aleksaj-vtool almost 2 years ago - 3 comments

#62 - Unable to run Simulation using FuseSoC

Issue - State: closed - Opened by vignajeth almost 2 years ago - 1 comment

#61 - Compilation Errors while running SweRVolf

Issue - State: closed - Opened by vignajeth almost 2 years ago - 1 comment

#60 - SweRV EL2 with External Sram memory issue

Issue - State: closed - Opened by nimra471 almost 2 years ago - 1 comment

#59 - Read access stops when read/write access is repeated

Issue - State: open - Opened by yafuru0 almost 2 years ago - 2 comments

#58 - Tested/Implemented on other cores

Issue - State: open - Opened by geoalx almost 2 years ago

#57 - fusesoc run --target=arty_a7 swervolf

Issue - State: closed - Opened by nimra471 almost 2 years ago - 1 comment

#56 - simple_spi.v file not found in the repository

Issue - State: closed - Opened by Sesib over 2 years ago - 1 comment

#55 - axi/wb bus cycle times

Issue - State: open - Opened by jamesbbecker over 2 years ago - 7 comments

#54 - Setup fails with error about cdc_utils

Issue - State: closed - Opened by paulcobb27 almost 3 years ago - 3 comments

#53 - Arty a7

Pull Request - State: closed - Opened by bl0x almost 3 years ago - 4 comments

#52 - Investigating cache performance with burst wrap reads

Issue - State: open - Opened by jeras almost 3 years ago

#52 - Investigating cache performance with burst wrap reads

Issue - State: open - Opened by jeras almost 3 years ago

#51 - fusesoc run --target=basys3 with vivado 2021.2

Issue - State: open - Opened by kendallgreen almost 3 years ago - 5 comments

#50 - Linux Compatibility

Issue - State: closed - Opened by SOUMYADIPSAHA10 about 3 years ago

#49 - Linux compatibility

Issue - State: closed - Opened by JOHNTBIJU about 3 years ago - 1 comment

#48 - Which are the steps to run baremetal c routines?

Issue - State: closed - Opened by kuoyaoming93 about 3 years ago - 1 comment

#47 - how to change the CPUs clock frequency

Issue - State: closed - Opened by kuoyaoming93 about 3 years ago - 2 comments

#46 - [Nexys4 DDR] Struggling to load into ICCM (address 0xEE000000)

Issue - State: open - Opened by mablinov about 3 years ago - 3 comments

#45 - hello_uart.S: Fix symbol label to point to string

Pull Request - State: closed - Opened by mablinov about 3 years ago - 1 comment

#44 - Running Compliance Test for Swerv

Issue - State: closed - Opened by YeuzhiHere about 3 years ago - 4 comments

#41 - fusesoc build and run using xcelium

Issue - State: closed - Opened by nikhill-agnisys over 3 years ago - 12 comments

#40 - fusesoc run --target=sim swervolf with Verilator=3.918

Issue - State: open - Opened by nicolast0604 over 3 years ago - 2 comments

#39 - fusesoc run --target=nexys_a7 swervolf with Vivado 2020.1

Issue - State: open - Opened by nicolast0604 over 3 years ago - 2 comments

#38 - fusesoc run --target=sim swervolf with verilator 4.104

Issue - State: closed - Opened by nicolast0604 over 3 years ago - 2 comments

#37 - Do you have any plan to support SweRV-EH2.

Issue - State: open - Opened by nicolast0604 over 3 years ago - 2 comments

#36 - LItedram Generation

Issue - State: closed - Opened by lindajames101 over 3 years ago - 3 comments

#35 - Boot Switches table error

Issue - State: closed - Opened by ddandare over 3 years ago - 1 comment

#34 - README: Point to the Tock port

Pull Request - State: closed - Opened by alistair23 over 3 years ago - 3 comments

#33 - Dectect unsupported features in core description files

Issue - State: closed - Opened by olofk over 3 years ago

#32 - Verilator compilation fail due to "common_cells/registers.vh" not found

Issue - State: closed - Opened by tomverbeure over 3 years ago - 8 comments

#31 - Fusesoc Simulation Error

Issue - State: open - Opened by mhamzaali almost 4 years ago - 1 comment

#30 - Swerv configuration & Swervolf

Issue - State: open - Opened by agrobman almost 4 years ago

#29 - bscan_tap module - how does it work?

Issue - State: open - Opened by agrobman almost 4 years ago - 21 comments

#28 - Do you have a plan to support SweRV-EL2 ?

Issue - State: closed - Opened by kidonglee almost 4 years ago - 4 comments

#27 - Add missing "expose_csrs" command to OpenOCD .cfg files

Pull Request - State: closed - Opened by JanMatCodasip about 4 years ago

#26 - debugging is not working !!!

Issue - State: open - Opened by kidonglee about 4 years ago - 12 comments

#25 - verilator + openocd + gdb simulation issue

Issue - State: open - Opened by kidonglee about 4 years ago

#24 - Error with "Build Zephyr applications"

Issue - State: closed - Opened by kidonglee about 4 years ago - 2 comments

#23 - Configure OpenOCD to utilize abstract mem. access

Pull Request - State: closed - Opened by JanMatCodasip about 4 years ago - 4 comments

#22 - nondeterministic and incorrect behavior of code ran over SweRVolf on Nexys-A7

Issue - State: closed - Opened by monniaux about 4 years ago - 19 comments

#21 - Unsupported board in build Zephyr applications

Issue - State: open - Opened by cst-kirank about 4 years ago - 6 comments

#20 - Running pre-compiled zephyr examples failed

Issue - State: closed - Opened by cst-kirank about 4 years ago - 2 comments

#19 - modifed the README for SweRV-EL2zybo

Pull Request - State: closed - Opened by altuSemi about 4 years ago

#18 - Adding a new target, configuring the el2 core

Issue - State: closed - Opened by altuSemi about 4 years ago - 1 comment

#17 - SImulation run error

Issue - State: closed - Opened by altuSemi about 4 years ago - 1 comment

#16 - VERSION_PATCH macro not defined

Issue - State: closed - Opened by luispimo over 4 years ago - 2 comments

#14 - Zephyr with adxl362 fails to compile

Issue - State: open - Opened by ddandare over 4 years ago - 1 comment

#13 - Updated OpenOCD .cfg files for proper ICACHE flush

Pull Request - State: closed - Opened by JanMatCodasip over 4 years ago - 5 comments

#12 - Riviera-PRO common compilation

Issue - State: closed - Opened by dawidzim over 4 years ago - 2 comments

#11 - Compilation failed for EH1 with Verilator

Issue - State: closed - Opened by tunghoang290780 over 4 years ago - 1 comment

#10 - Replace deprecated AXI infrastructure

Issue - State: closed - Opened by olofk over 4 years ago - 6 comments

#9 - Verilog testbench updated to support newer jtag_vpi:0-r5.

Pull Request - State: closed - Opened by JanMatCodasip over 4 years ago - 3 comments

#8 - Write Buffer coalescing in compliance tests

Issue - State: closed - Opened by Podgorny98 over 4 years ago - 3 comments

#7 - added missing compilation mode in core

Pull Request - State: closed - Opened by dawidzim over 4 years ago - 1 comment

#6 - support for Riviera-PRO

Pull Request - State: closed - Opened by dawidzim over 4 years ago - 3 comments

#5 - Incompatible modport connection in axi_node_wrap_with_slives

Issue - State: closed - Opened by dawidzim over 4 years ago - 2 comments

#4 - Is it OK to simulate under VCS?

Issue - State: closed - Opened by zhanjf about 5 years ago - 13 comments

#3 - error during run simulation

Issue - State: closed - Opened by zhanjf about 5 years ago - 1 comment

#2 - Synthesis fails on Vivado 2019.1

Issue - State: closed - Opened by kammoh about 5 years ago - 9 comments

#1 - Compilation error

Issue - State: closed - Opened by tunghoang290780 about 5 years ago - 3 comments