chipsalliance/cores-veer-el2 issues and pull requests

#89 - Add RISCOF tests

Pull Request - State: closed - Opened by mkurc-ant over 1 year ago

#88 - Next PC not sampled when core wakes up from sleep in Verilator run

Issue - State: open - Opened by upadhyayulakiran over 1 year ago - 4 comments

#87 - [do not merge] WIP test module

Pull Request - State: closed - Opened by mczyz-antmicro over 1 year ago

#86 - Coverage reporting

Pull Request - State: closed - Opened by mkurc-ant over 1 year ago

#85 - Add missing el2_pkg package imports

Pull Request - State: closed - Opened by mkurc-ant over 1 year ago

#84 - Integrate main-next

Pull Request - State: closed - Opened by mkurc-ant over 1 year ago

#83 - Implement PyUVM/cocotb/Verilator verification environment

Pull Request - State: closed - Opened by mczyz-antmicro over 1 year ago

#82 - Add Renode test case to RISC-V DV CI

Pull Request - State: closed - Opened by mczyz-antmicro over 1 year ago

#81 - Add cocotb-based testing environment

Pull Request - State: closed - Opened by koluckirafal over 1 year ago - 1 comment

#80 - Fix quickstart with verilator

Pull Request - State: closed - Opened by Risto97 over 1 year ago - 3 comments

#79 - Use RISC-V DV for core verification

Pull Request - State: closed - Opened by mkurc-ant over 1 year ago

#78 - Add cocotb verification environment

Pull Request - State: closed - Opened by koluckirafal over 1 year ago - 1 comment

#77 - Fix swapped mnemonics

Pull Request - State: closed - Opened by mkurc-ant over 1 year ago

#76 - Correction of default WIDTH param value of rvdffppe

Pull Request - State: closed - Opened by mkurc-ant over 1 year ago

#75 - Implement script to evaluate lint and format compliance

Pull Request - State: closed - Opened by mczyz-antmicro over 1 year ago - 2 comments

#74 - Manual fixes of selected issues raised by lint

Pull Request - State: closed - Opened by mczyz-antmicro over 1 year ago

#73 - rvdffppe elab issue

Issue - State: closed - Opened by howardtr over 1 year ago - 1 comment

#72 - Move formatter and linter workflows from two-stage setup

Pull Request - State: closed - Opened by koluckirafal over 1 year ago

#71 - Update canned hex

Pull Request - State: closed - Opened by mczyz-antmicro over 1 year ago

#70 - Fix push trigger in PR use case, add flow for maintenance of main branch

Pull Request - State: closed - Opened by mczyz-antmicro over 1 year ago - 1 comment

#69 - Run all tests in CI

Pull Request - State: closed - Opened by mkurc-ant over 1 year ago

#68 - [do not merge] Test module

Pull Request - State: closed - Opened by mczyz-antmicro over 1 year ago - 1 comment

#67 - Update format jobs to match trigger style and align names

Pull Request - State: closed - Opened by mczyz-antmicro over 1 year ago

#66 - Move action from main to maintenance branch

Pull Request - State: closed - Opened by mczyz-antmicro over 1 year ago - 1 comment

#65 - [DO NOT MERGE] Linting test

Pull Request - State: closed - Opened by koluckirafal over 1 year ago

#64 - Add Verible linter action

Pull Request - State: closed - Opened by koluckirafal over 1 year ago

#63 - Basic CI

Pull Request - State: closed - Opened by mkurc-ant over 1 year ago

#62 - Add CI verible formatter action

Pull Request - State: closed - Opened by mczyz-antmicro over 1 year ago

#61 - External scan-chain reset control

Pull Request - State: closed - Opened by mkurc-ant almost 2 years ago

#60 - Remove VERILATOR ifdefs, use updated Verilator

Pull Request - State: closed - Opened by mkurc-ant almost 2 years ago - 1 comment

#59 - VeeR defines uniquification

Issue - State: open - Opened by nstewart-amd almost 2 years ago

#58 - RV_ASSERT_ON is always enabled

Issue - State: open - Opened by nstewart-amd almost 2 years ago - 5 comments

#57 - EL2 Memory Interface Synthesis Compatibility

Issue - State: open - Opened by nstewart-amd almost 2 years ago

#56 - Allow injecting user synchronization modules

Pull Request - State: closed - Opened by mkurc-ant almost 2 years ago - 4 comments

#55 - Added a possibility to inject RV_ASSERT_ON definition via config options

Pull Request - State: closed - Opened by mkurc-ant almost 2 years ago - 1 comment

#54 - Add a way of injecting user module for clock gate(s)

Pull Request - State: closed - Opened by mkurc-ant almost 2 years ago - 1 comment

#53 - Adds value parsing to text_in_iccm argument

Pull Request - State: closed - Opened by JohannesKutning almost 2 years ago - 1 comment

#52 - DFT overrides after any logic on resets

Issue - State: closed - Opened by rahuljainNV almost 2 years ago - 6 comments

#51 - synchronizers implemented as synthesizable flops

Issue - State: open - Opened by rahuljainNV almost 2 years ago - 3 comments

#50 - Replacing hand instantiated clock gate cells

Issue - State: open - Opened by rahuljainNV almost 2 years ago - 9 comments

#49 - Hiding assertions code from design tools

Issue - State: open - Opened by rahuljainNV almost 2 years ago - 12 comments

#48 - Added support for RISCOF Compliance Testing

Pull Request - State: closed - Opened by ALI11-2000 about 2 years ago - 1 comment

#47 - Undriven 'mask' signal in the PIC ctrl module

Issue - State: closed - Opened by calebofearth over 2 years ago - 2 comments

#46 - Synthesis dc_shell giving error while reading: parameter el2_param_t pt = '{

Issue - State: closed - Opened by rahulsharmab over 2 years ago - 7 comments

#45 - RISC-V COMPLIANCE RUNNING ON SweRV El2

Issue - State: closed - Opened by KinzaQamar over 2 years ago

#44 - DCCM Region 0x0008_0000

Issue - State: closed - Opened by KinzaQamar over 2 years ago - 1 comment

#43 - RISC-V compliance on EL2

Issue - State: closed - Opened by KinzaQamar over 2 years ago - 3 comments

#42 - srai srli opcode swap in SweRV

Issue - State: closed - Opened by RehanEjaz over 2 years ago - 3 comments

#41 - Error: unrecognized opcode csrw

Issue - State: closed - Opened by kuoyaoming93 over 2 years ago - 1 comment

#40 - branch prediction understanding

Issue - State: open - Opened by KinzaQamar over 2 years ago

#39 - display statement in el2_ifu.sv

Issue - State: open - Opened by KinzaQamar over 2 years ago - 6 comments

#38 - Machine Timer Interrupt

Issue - State: closed - Opened by HamzaShabbir517 almost 3 years ago - 8 comments

#37 - understanding Branch Prediction

Issue - State: open - Opened by KinzaQamar almost 3 years ago - 2 comments

#36 - How to fix load region prediction error

Issue - State: closed - Opened by wenjiegong about 3 years ago - 5 comments

#35 - PIC Configuration

Issue - State: closed - Opened by HamzaShabbir517 about 3 years ago - 21 comments

#34 - Internal timer interrupt service routine

Issue - State: closed - Opened by RehanEjaz about 3 years ago - 2 comments

#33 - SweRV EL2 test comparison with whisper ISS

Issue - State: closed - Opened by HamzaShabbir517 about 3 years ago - 10 comments

#32 - Synthesising the EL2 for a Intel Cyclone 10 GX FPGA

Issue - State: closed - Opened by davidp135 over 3 years ago - 26 comments

#31 - Synthesis error using Vivado 2017.4

Issue - State: closed - Opened by asadaleem-lm over 3 years ago - 3 comments

#30 - Debug Module

Issue - State: closed - Opened by HamzaShabbir517 over 3 years ago - 1 comment

#29 - pd_defines.vh

Issue - State: closed - Opened by HamzaShabbir517 over 3 years ago - 2 comments

#28 - Pre-load Task in testbench

Issue - State: closed - Opened by HamzaShabbir517 over 3 years ago - 4 comments

#27 - Is your RAMs define in mem_lib.sv is synthesizeable

Issue - State: closed - Opened by HamzaShabbir517 over 3 years ago - 2 comments

#26 - Update Riviera-PRO makefile

Pull Request - State: closed - Opened by dawidzim over 3 years ago

#25 - Feature request: Formal Verification of SweRV-EL2 using the open source riscv-formal tool

Issue - State: closed - Opened by ShashankVM over 3 years ago

#24 - Debug support

Issue - State: closed - Opened by olofk over 3 years ago - 2 comments

#23 - Testbenches don't work for typical_pd using verilator

Issue - State: closed - Opened by kuoyaoming93 over 3 years ago - 3 comments

#22 - How to configure to reach 4.3 in the CoreMark test

Issue - State: closed - Opened by tsuijian over 3 years ago - 1 comment

#21 - How is store after faulting load handled?

Issue - State: closed - Opened by Silabs-ArjanB almost 4 years ago - 2 comments

#20 - Update FuseSoC SweRV config generator

Pull Request - State: closed - Opened by olofk almost 4 years ago - 1 comment

#19 - About ID

Issue - State: closed - Opened by Jupitor1 almost 4 years ago - 2 comments

#18 - critical path is from DCCM to ICCM ？

Issue - State: open - Opened by yzt000000 about 4 years ago - 1 comment

#17 - Fixes in riviera support which was pushed onto 1.3 version

Pull Request - State: closed - Opened by danielmlynek about 4 years ago - 5 comments

#16 - Synthesis clock speed is very slow

Issue - State: open - Opened by kidonglee about 4 years ago - 6 comments

#15 - synthesis errors

Issue - State: closed - Opened by kidonglee about 4 years ago - 2 comments

#14 - synthesis script template

Issue - State: closed - Opened by kidonglee about 4 years ago - 2 comments

#13 - cmark scores

Issue - State: closed - Opened by kidonglee about 4 years ago - 4 comments

#12 - coremark simulation results

Issue - State: closed - Opened by kidonglee about 4 years ago - 3 comments

#11 - Changes needed for Riviera simulator 2020.04

Pull Request - State: closed - Opened by danielmlynek about 4 years ago - 2 comments

#10 - Fix typo in swerv.config causing wrong unsets to be printed

Pull Request - State: closed - Opened by olofk about 4 years ago - 1 comment

#9 - Mem lib fix

Pull Request - State: closed - Opened by olofk about 4 years ago - 1 comment

#8 - ROM for EL2

Issue - State: open - Opened by altuSemi over 4 years ago

#7 - Update version in core description file

Pull Request - State: closed - Opened by olofk over 4 years ago - 1 comment

#6 - [HDL 9-849]

Issue - State: closed - Opened by altuSemi over 4 years ago - 5 comments

#5 - Question: ASIC synthesis flow

Issue - State: closed - Opened by nagendragd over 4 years ago - 2 comments

#4 - FuseSoC and Github Linter Action

Pull Request - State: closed - Opened by wallento over 4 years ago - 15 comments

GitHub / chipsalliance/cores-veer-el2 issues and pull requests