chipsalliance/cores-veer-eh2 issues and pull requests

#44 - Debug code cleanup

Pull Request - State: open - Opened by oliverbm67 3 months ago

#43 - How to config and dump the HPM for profiling?

Issue - State: closed - Opened by zhongchengyong 4 months ago - 2 comments

#42 - dhry_mt benchmark failed

Issue - State: open - Opened by chchenl 6 months ago

#41 - how to modify the tb file

Issue - State: closed - Opened by huge12138 over 1 year ago

#40 - Repeated entry interrupt

Issue - State: open - Opened by luis-han255 almost 2 years ago

#39 - PreSync/PostSync in CSR Registers

Issue - State: open - Opened by vignajeth over 2 years ago

#38 - Adding FPU with EH2

Issue - State: open - Opened by zeeshanrafique23 over 2 years ago - 6 comments

#37 - AXI Assertion Bug

Issue - State: open - Opened by vignajeth over 2 years ago

#36 - VerilatorTB problem

Issue - State: open - Opened by togetherwhenyouwant over 2 years ago - 1 comment

#35 - Part signals of DMA have not load.

Issue - State: open - Opened by JLstore almost 3 years ago

#34 - RISCV compliance test suit partly fails

Issue - State: closed - Opened by Don-Haugaard almost 3 years ago - 1 comment

#33 - [Question] AXI4-ectomy

Issue - State: closed - Opened by michael-etzkorn almost 3 years ago - 2 comments

#32 - No improvement for Statistics

Issue - State: open - Opened by samfishman1 almost 3 years ago - 5 comments

#31 - understanding of axi_lsu_dma_bridge

Issue - State: closed - Opened by vignajeth almost 3 years ago - 2 comments

#30 - range vs region

Issue - State: closed - Opened by vignajeth about 3 years ago - 1 comment

#29 - meaning of lus_p.pipe and lsu.stack

Issue - State: open - Opened by vignajeth about 3 years ago

#28 - unused lsu_cmpen_dc2 signal

Issue - State: closed - Opened by vignajeth about 3 years ago - 1 comment

#27 - doubt in ld_full_hit_lo/hi_dc2

Issue - State: closed - Opened by vignajeth about 3 years ago - 2 comments

#26 - number of instr buffer mentioned in PRM

Issue - State: closed - Opened by vignajeth about 3 years ago - 1 comment

#25 - understanding store_databypass_c1 and c2

Issue - State: closed - Opened by vignajeth about 3 years ago - 3 comments

#24 - unused csr_perfv{a to i} in decoder

Issue - State: closed - Opened by vignajeth about 3 years ago - 2 comments

#23 - Working of Non-Blocking Loads

Issue - State: closed - Opened by vignajeth about 3 years ago - 3 comments

#22 - Can't execute "coredecode -in decode > coredecode.e"

Issue - State: open - Opened by Jeremy-Jia about 3 years ago - 9 comments

#21 - Importance of ldst_dual signals

Issue - State: closed - Opened by vignajeth about 3 years ago - 1 comment

#20 - understanding I-Cache

Issue - State: closed - Opened by vignajeth about 3 years ago - 3 comments

#19 - multi thread cache miss question

Issue - State: open - Opened by S-Nomii about 3 years ago - 1 comment

#18 - Core Design validation/verification

Issue - State: open - Opened by SyoAnd over 3 years ago - 1 comment

#17 - ICCM read issue

Issue - State: closed - Opened by JLstore over 3 years ago - 2 comments

#16 - Core synthesis

Issue - State: closed - Opened by Saqlinahamad over 3 years ago - 31 comments

#15 - Cores-SweRV-EH2 Lint error

Issue - State: closed - Opened by JLstore over 3 years ago - 7 comments

#14 - Which config would match the result of 6-7 coremark/Mhz

Issue - State: closed - Opened by pengwubj over 3 years ago - 2 comments

#13 - Hex files for dhry tests are not updated after related source files changes

Issue - State: closed - Opened by danielmlynek over 3 years ago - 14 comments

#12 - Riviera support trivial fixes

Pull Request - State: closed - Opened by danielmlynek over 3 years ago

#11 - build error with target=high_perf

Issue - State: closed - Opened by kidonglee about 4 years ago - 14 comments

#10 - ICCM Only Mode (How does ICCM talks to External Memory)

Issue - State: closed - Opened by HamzaShabbir517 about 4 years ago - 3 comments

#9 - LSU bus buffer code

Issue - State: closed - Opened by rsunkam about 4 years ago - 3 comments

#8 - Changes needed for Riviera simulator

Pull Request - State: closed - Opened by danielmlynek about 4 years ago - 29 comments

#7 - Verilator build is erroring out

Issue - State: closed - Opened by irfanwaheed over 4 years ago - 1 comment

#6 - AHB-Lite support

Issue - State: closed - Opened by qq27303272 over 4 years ago - 3 comments

#5 - Hardware Accelerator and its interface.

Issue - State: closed - Opened by zeeshanrafique23 over 4 years ago - 1 comment

#4 - Block diagram is missing.

Issue - State: closed - Opened by zeeshanrafique23 over 4 years ago - 2 comments

#3 - Fix UNOPTFLAT warning on dccm_wr_data_lo/hi. No functional change.

Pull Request - State: open - Opened by wsnyder almost 5 years ago

#2 - Add cmark.hex

Issue - State: closed - Opened by wsnyder almost 5 years ago - 1 comment

#1 - Support TEST=<name>.hex to fix defaulting to hex files when no RISCV tools

Pull Request - State: closed - Opened by wsnyder almost 5 years ago

GitHub / chipsalliance/cores-veer-eh2 issues and pull requests