Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / chipsalliance/cores-veer-eh1 issues and pull requests

#38 - DCCM coherncy issue

Issue - State: closed - Opened by taddevrp almost 5 years ago - 2 comments

#37 - Question: how to disable (bypass) data checks in cache?

Issue - State: closed - Opened by vit82 almost 5 years ago - 2 comments

#37 - Question: how to disable (bypass) data checks in cache?

Issue - State: closed - Opened by vit82 almost 5 years ago - 2 comments

#36 - DCCM load/store conflict situation

Issue - State: closed - Opened by taddevrp almost 5 years ago - 14 comments

#36 - DCCM load/store conflict situation

Issue - State: closed - Opened by taddevrp almost 5 years ago - 14 comments

#35 - running with stack in RAM

Issue - State: closed - Opened by monniaux almost 5 years ago - 5 comments

#35 - running with stack in RAM

Issue - State: closed - Opened by monniaux almost 5 years ago - 5 comments

#34 - Auto increment is broken for system bus accesses of 64 bit.

Issue - State: closed - Opened by joeski65 almost 5 years ago - 1 comment

#34 - Auto increment is broken for system bus accesses of 64 bit.

Issue - State: closed - Opened by joeski65 almost 5 years ago - 1 comment

#33 - RISCV-Compliance check - Some Fails

Issue - State: closed - Opened by cr8601 almost 5 years ago - 8 comments

#33 - RISCV-Compliance check - Some Fails

Issue - State: closed - Opened by cr8601 almost 5 years ago - 8 comments

#32 - EH2 and EL2 are missing.

Issue - State: closed - Opened by pieter3d almost 5 years ago - 1 comment

#32 - EH2 and EL2 are missing.

Issue - State: closed - Opened by pieter3d almost 5 years ago - 1 comment

#31 - RV core With AHB bus will cause bug when send read operation

Issue - State: closed - Opened by walkingjian almost 5 years ago - 1 comment

#31 - RV core With AHB bus will cause bug when send read operation

Issue - State: closed - Opened by walkingjian almost 5 years ago - 1 comment

#30 - Make for riviera

Pull Request - State: closed - Opened by danielmlynek almost 5 years ago - 3 comments

#30 - Make for riviera

Pull Request - State: closed - Opened by danielmlynek almost 5 years ago - 3 comments

#29 - Fixed FPGA build error

Pull Request - State: closed - Opened by arupde171 almost 5 years ago

#28 - Software breakpoints with OpenOCD + GDB

Issue - State: closed - Opened by cstewart-ust almost 5 years ago - 3 comments

#27 - Spacing and include cleanup

Pull Request - State: closed - Opened by pieter3d about 5 years ago - 1 comment

#27 - Spacing and include cleanup

Pull Request - State: closed - Opened by pieter3d about 5 years ago - 1 comment

#26 - Issue in running the Design in vivado

Issue - State: closed - Opened by rajat-agnisys about 5 years ago - 1 comment

#26 - Issue in running the Design in vivado

Issue - State: closed - Opened by rajat-agnisys about 5 years ago - 1 comment

#25 - Add test for core & simulator benchmarking

Issue - State: closed - Opened by wsnyder about 5 years ago - 4 comments

#25 - Add test for core & simulator benchmarking

Issue - State: closed - Opened by wsnyder about 5 years ago - 4 comments

#24 - Interrupt example

Issue - State: closed - Opened by Jagannaths3 about 5 years ago - 1 comment

#24 - Interrupt example

Issue - State: closed - Opened by Jagannaths3 about 5 years ago - 1 comment

#23 - ifu interface access illegal address

Issue - State: closed - Opened by Chuanjieliu about 5 years ago - 1 comment

#23 - ifu interface access illegal address

Issue - State: closed - Opened by Chuanjieliu about 5 years ago - 1 comment

#22 - Unconventional mux logic

Issue - State: closed - Opened by saw235 about 5 years ago - 7 comments

#22 - Unconventional mux logic

Issue - State: closed - Opened by saw235 about 5 years ago - 7 comments

#21 - Add initial FuseSoC support

Pull Request - State: closed - Opened by olofk about 5 years ago

#21 - Add initial FuseSoC support

Pull Request - State: closed - Opened by olofk about 5 years ago

#20 - Add Travis CI

Pull Request - State: closed - Opened by toddstrader about 5 years ago

#20 - Add Travis CI

Pull Request - State: closed - Opened by toddstrader about 5 years ago

#19 - Questa support in Makefile for simulations

Issue - State: closed - Opened by svenka3 about 5 years ago - 2 comments

#19 - Questa support in Makefile for simulations

Issue - State: closed - Opened by svenka3 about 5 years ago - 2 comments

#18 - Initialization/startup sequence and linker script for large C programs

Issue - State: closed - Opened by dareyouspam about 5 years ago - 1 comment

#18 - Initialization/startup sequence and linker script for large C programs

Issue - State: closed - Opened by dareyouspam about 5 years ago - 1 comment

#17 - Supporting DCCM without multi-bank Support

Issue - State: closed - Opened by Jagannaths3 about 5 years ago - 1 comment

#17 - Supporting DCCM without multi-bank Support

Issue - State: closed - Opened by Jagannaths3 about 5 years ago - 1 comment

#16 - DCCM max size

Issue - State: closed - Opened by Jagannaths3 about 5 years ago - 1 comment

#16 - DCCM max size

Issue - State: closed - Opened by Jagannaths3 about 5 years ago - 1 comment

#15 - Boot code from iccm

Issue - State: closed - Opened by milk0920 about 5 years ago - 7 comments

#15 - Boot code from iccm

Issue - State: closed - Opened by milk0920 about 5 years ago - 7 comments

#14 - Issues to enable DMA for SweRV

Issue - State: closed - Opened by rajoogupta about 5 years ago - 7 comments

#14 - Issues to enable DMA for SweRV

Issue - State: closed - Opened by rajoogupta about 5 years ago - 7 comments

#13 - Testbench does not verilate

Issue - State: closed - Opened by toddstrader over 5 years ago - 2 comments

#12 - Fix beh_lib.sv syntax error when using RV_FPGA_OPTIMIZE

Pull Request - State: closed - Opened by olofk over 5 years ago - 4 comments

#11 - SweRV VLNV

Issue - State: closed - Opened by olofk over 5 years ago - 2 comments

#10 - Move JTAG TAP to swerv_wrapper

Pull Request - State: closed - Opened by olofk over 5 years ago - 3 comments

#9 - SweRV build breaks on latest Verilator

Issue - State: closed - Opened by toddstrader over 5 years ago - 3 comments

#8 - freeRTOS on SweRB

Issue - State: closed - Opened by ycyang0508 over 5 years ago - 1 comment

#7 - Improve reference to espresso on front page?

Issue - State: closed - Opened by trayres over 5 years ago - 1 comment

#6 - flist.questa includes def.sv and hasn't moved to testbench dir

Issue - State: closed - Opened by ChippendaleMupp over 5 years ago - 1 comment

#4 - Apostrophe incorrectly introduced into the licence header ifu_ic_mem.sv

Issue - State: closed - Opened by ChippendaleMupp over 5 years ago - 1 comment

#3 - Code cleanup: replace spurious tabs with spaces

Issue - State: closed - Opened by ChippendaleMupp over 5 years ago - 1 comment

#2 - Code cleanup: fix line endings

Issue - State: closed - Opened by ChippendaleMupp over 5 years ago - 1 comment

#1 - What is the difference?

Issue - State: closed - Opened by hyf6661669 over 5 years ago - 1 comment