chipsalliance/cores-veer-eh1 issues and pull requests

#100 - fpga_optimize cannot be set to 0 in swerv_config

Issue - State: open - Opened by jlucnagel over 3 years ago - 1 comment

#100 - fpga_optimize cannot be set to 0 in swerv_config

Issue - State: open - Opened by jlucnagel over 3 years ago - 1 comment

#99 - slip in dec_decode_ctrl

Issue - State: closed - Opened by kuangxin over 3 years ago

#99 - slip in dec_decode_ctrl

Issue - State: closed - Opened by kuangxin over 3 years ago

#98 - Timing violations with Vivado

Issue - State: closed - Opened by Rusty-Wire over 3 years ago - 4 comments

#98 - Timing violations with Vivado

Issue - State: closed - Opened by Rusty-Wire over 3 years ago - 4 comments

#97 - $readmem file address beyond bounds of array

Issue - State: closed - Opened by HamzaShabbir517 over 3 years ago - 8 comments

#97 - $readmem file address beyond bounds of array

Issue - State: closed - Opened by HamzaShabbir517 over 3 years ago - 8 comments

#96 - GCC version in Makefile

Issue - State: closed - Opened by qian-gu over 3 years ago - 4 comments

#96 - GCC version in Makefile

Issue - State: closed - Opened by qian-gu over 3 years ago - 4 comments

#95 - Formal Verification of SweRV EH1 using riscv-formal

Issue - State: closed - Opened by ShashankVM over 3 years ago

#94 - Fix FuseSoC config generator

Pull Request - State: closed - Opened by joannabrozek over 3 years ago - 8 comments

#94 - Fix FuseSoC config generator

Pull Request - State: closed - Opened by joannabrozek over 3 years ago - 8 comments

#93 - Declare variables before using them

Pull Request - State: closed - Opened by tgorochowik almost 4 years ago - 1 comment

#93 - Declare variables before using them

Pull Request - State: closed - Opened by tgorochowik almost 4 years ago - 1 comment

#92 - cmark_dccm fails to build

Issue - State: closed - Opened by danielmlynek almost 4 years ago - 3 comments

#92 - cmark_dccm fails to build

Issue - State: closed - Opened by danielmlynek almost 4 years ago - 3 comments

#91 - No tags for releases

Issue - State: closed - Opened by robtaylor almost 4 years ago - 5 comments

#90 - tlu_flush_path_e4

Issue - State: open - Opened by kingstone1927 almost 4 years ago - 7 comments

#89 - Remove unused scan_mode input from dmi_wrapper

Pull Request - State: closed - Opened by olofk almost 4 years ago

#89 - Remove unused scan_mode input from dmi_wrapper

Pull Request - State: closed - Opened by olofk almost 4 years ago

#88 - which unit control flushing of the pipelines?

Issue - State: closed - Opened by kingstone1927 almost 4 years ago - 3 comments

#88 - which unit control flushing of the pipelines?

Issue - State: closed - Opened by kingstone1927 almost 4 years ago - 3 comments

#87 - print instruction to exec.log

Issue - State: closed - Opened by kingstone1927 almost 4 years ago - 2 comments

#87 - print instruction to exec.log

Issue - State: closed - Opened by kingstone1927 almost 4 years ago - 2 comments

#86 - Stall point

Issue - State: closed - Opened by kingstone1927 almost 4 years ago - 5 comments

#85 - Delay after fetching instructions when not using icache

Issue - State: closed - Opened by crazy-catlady almost 4 years ago - 4 comments

#85 - Delay after fetching instructions when not using icache

Issue - State: closed - Opened by crazy-catlady almost 4 years ago - 4 comments

#84 - Set default mrac value with swerv.config

Issue - State: open - Opened by olofk almost 4 years ago - 1 comment

#83 - How can I debug using Verilator and gdb

Issue - State: closed - Opened by kingstone1927 almost 4 years ago - 6 comments

#82 - Only load Vivado TCL files when using Vivado

Pull Request - State: closed - Opened by olofk about 4 years ago

#81 - Macro definitions not being found

Issue - State: closed - Opened by rlb1116 about 4 years ago - 2 comments

#81 - Macro definitions not being found

Issue - State: closed - Opened by rlb1116 about 4 years ago - 2 comments

#80 - Can I integrate the Cores-SweRV on Zedboard fpga?

Issue - State: closed - Opened by kingstone1927 about 4 years ago - 1 comment

#80 - Can I integrate the Cores-SweRV on Zedboard fpga?

Issue - State: closed - Opened by kingstone1927 about 4 years ago - 1 comment

#79 - question about adding custom instructions

Issue - State: closed - Opened by feiger313 about 4 years ago - 2 comments

#78 - Speculative load observed on LSU AXI

Issue - State: closed - Opened by pieter3d about 4 years ago - 10 comments

#78 - Speculative load observed on LSU AXI

Issue - State: closed - Opened by pieter3d about 4 years ago - 10 comments

#77 - NMI HELP

Issue - State: closed - Opened by Richard2088 about 4 years ago - 1 comment

#77 - NMI HELP

Issue - State: closed - Opened by Richard2088 about 4 years ago - 1 comment

#76 - Set snapshot dir to a known location in FuseSoC SweRV config generator

Pull Request - State: closed - Opened by olofk about 4 years ago - 1 comment

#75 - Adapt FuseSoC SweRV config generator wrt new snapshot dir

Pull Request - State: closed - Opened by olofk about 4 years ago - 1 comment

#74 - mcontrol chain bit not WARL on triggers 1 & 3

Issue - State: closed - Opened by wronkiew-ghs about 4 years ago - 3 comments

#74 - mcontrol chain bit not WARL on triggers 1 & 3

Issue - State: closed - Opened by wronkiew-ghs about 4 years ago - 3 comments

#73 - pic

Issue - State: closed - Opened by S-Nomii about 4 years ago - 5 comments

#73 - pic

Issue - State: closed - Opened by S-Nomii about 4 years ago - 5 comments

#72 - The CSR mepc cann't save correct mret address after Continuous NMI happened

Issue - State: closed - Opened by Richard2088 about 4 years ago - 23 comments

#72 - The CSR mepc cann't save correct mret address after Continuous NMI happened

Issue - State: closed - Opened by Richard2088 about 4 years ago - 23 comments

#71 - dccm initialization

Issue - State: closed - Opened by S-Nomii about 4 years ago - 3 comments

#70 - typo in swerv.config

Issue - State: closed - Opened by sobuch over 4 years ago - 4 comments

#69 - Cores-SweRV development planning

Issue - State: closed - Opened by zhuzhizhan over 4 years ago - 8 comments

#68 - Update SweRV version in core description file to 1.7

Pull Request - State: closed - Opened by olofk over 4 years ago

#67 - Which signal should I choose to trace Load/Store/pipeline state

Issue - State: closed - Opened by ymlei over 4 years ago - 1 comment

#67 - Which signal should I choose to trace Load/Store/pipeline state

Issue - State: closed - Opened by ymlei over 4 years ago - 1 comment

#66 - Determine size of i-cache

Issue - State: closed - Opened by wronkiew-ghs over 4 years ago - 2 comments

#66 - Determine size of i-cache

Issue - State: closed - Opened by wronkiew-ghs over 4 years ago - 2 comments

#65 - Erasing pending bits for interrupts

Issue - State: closed - Opened by albertodbg over 4 years ago - 25 comments

#65 - Erasing pending bits for interrupts

Issue - State: closed - Opened by albertodbg over 4 years ago - 25 comments

#64 - Always output 0 as the first bit of a DR bypass scan, per the 1149.1 …

Pull Request - State: closed - Opened by elindberg-ghs over 4 years ago - 9 comments

#64 - Always output 0 as the first bit of a DR bypass scan, per the 1149.1 …

Pull Request - State: closed - Opened by elindberg-ghs over 4 years ago - 9 comments

#63 - $readmem file address beyond bounds of array

Issue - State: closed - Opened by cebaut over 4 years ago - 6 comments

#63 - $readmem file address beyond bounds of array

Issue - State: closed - Opened by cebaut over 4 years ago - 6 comments

#62 - Added VCP switch for temporary solution for issue #61

Pull Request - State: closed - Opened by dawidzim over 4 years ago - 1 comment

#62 - Added VCP switch for temporary solution for issue #61

Pull Request - State: closed - Opened by dawidzim over 4 years ago - 1 comment

#61 - Wrong assignment to enum variable from expression of different type

Issue - State: closed - Opened by dawidzim over 4 years ago - 1 comment

#60 - Add GitHub repository topics

Issue - State: closed - Opened by dominiksalvet over 4 years ago - 3 comments

#60 - Add GitHub repository topics

Issue - State: closed - Opened by dominiksalvet over 4 years ago - 3 comments

#59 - problem with the linker and undefined reference errors ?

Issue - State: closed - Opened by mikemusasa over 4 years ago - 3 comments

#59 - problem with the linker and undefined reference errors ?

Issue - State: closed - Opened by mikemusasa over 4 years ago - 3 comments

#58 - question regarding how to run own C code on the core

Issue - State: closed - Opened by mikemusasa over 4 years ago - 1 comment

#57 - verilator in the make file not working

Issue - State: closed - Opened by mikemusasa over 4 years ago - 7 comments

#56 - Set RV_FPGA_OPTIMIZE by default?

Issue - State: closed - Opened by wsnyder over 4 years ago - 2 comments

#55 - update swerv.core for Riviera-PRO

Pull Request - State: closed - Opened by dawidzim over 4 years ago

#54 - Problem with interrupts and SweRVolf

Issue - State: closed - Opened by albertodbg over 4 years ago - 9 comments

#53 - access dccm through dma port

Issue - State: closed - Opened by qq27303272 over 4 years ago - 1 comment

#53 - access dccm through dma port

Issue - State: closed - Opened by qq27303272 over 4 years ago - 1 comment

#52 - Performance of SWERV EH1

Issue - State: closed - Opened by hyf6661669 over 4 years ago - 1 comment

#51 - About OpenOCD extensions

Issue - State: closed - Opened by linuxbest over 4 years ago - 3 comments

#51 - About OpenOCD extensions

Issue - State: closed - Opened by linuxbest over 4 years ago - 3 comments

#50 - external interrupt handler return problem

Issue - State: closed - Opened by vit82 over 4 years ago - 6 comments

#49 - fix for assignment to enum variable from expression of different type

Pull Request - State: closed - Opened by dawidzim over 4 years ago - 3 comments

#49 - fix for assignment to enum variable from expression of different type

Pull Request - State: closed - Opened by dawidzim over 4 years ago - 3 comments

#48 - SweRV on genesys2

Issue - State: closed - Opened by wehob over 4 years ago - 16 comments

#48 - SweRV on genesys2

Issue - State: closed - Opened by wehob over 4 years ago - 16 comments

#47 - D-cache to complement I-cache

Issue - State: closed - Opened by cahz over 4 years ago - 1 comment

#47 - D-cache to complement I-cache

Issue - State: closed - Opened by cahz over 4 years ago - 1 comment

#46 - SWERV CPU doesn't work properly if memory interface HREADY signal is high by default

Issue - State: closed - Opened by vit82 over 4 years ago - 4 comments

#46 - SWERV CPU doesn't work properly if memory interface HREADY signal is high by default

Issue - State: closed - Opened by vit82 over 4 years ago - 4 comments

#45 - Build Verilator without --trace support unless debug given.

Pull Request - State: closed - Opened by wsnyder almost 5 years ago - 1 comment

#45 - Build Verilator without --trace support unless debug given.

Pull Request - State: closed - Opened by wsnyder almost 5 years ago - 1 comment

#44 - Problems when using SweRV_fpga with V1.5 of SweRV

Issue - State: closed - Opened by danidep02 almost 5 years ago - 3 comments

#43 - Change address of programm

Issue - State: closed - Opened by MatthPouss07 almost 5 years ago - 1 comment

#42 - Riviera simulator added to Readme

Pull Request - State: closed - Opened by danielmlynek almost 5 years ago - 1 comment

#42 - Riviera simulator added to Readme

Pull Request - State: closed - Opened by danielmlynek almost 5 years ago - 1 comment

GitHub / chipsalliance/cores-veer-eh1 issues and pull requests