Ecosyste.ms: Issues

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GitHub / chipsalliance/aib-phy-hardware issues and pull requests

#26 - Cleanup

Pull Request - State: closed - Opened by dkehlet over 4 years ago

#24 - AIB Usage Note needs updates to examples for por and device detect

Issue - State: closed - Opened by dkehlet over 4 years ago - 3 comments

#24 - AIB Usage Note needs updates to examples for por and device detect

Issue - State: closed - Opened by dkehlet over 4 years ago - 3 comments

#23 - Issue #21 re: doc

Pull Request - State: closed - Opened by dkehlet over 4 years ago

#23 - Issue #21 re: doc

Pull Request - State: closed - Opened by dkehlet over 4 years ago

#22 - Added constraints (experimental)

Pull Request - State: closed - Opened by dkehlet over 4 years ago

#22 - Added constraints (experimental)

Pull Request - State: closed - Opened by dkehlet over 4 years ago

#21 - Table 5 of AIB_Usage_Note_v1_2_2.pdf has errors in *adapter_rstn signal names

Issue - State: closed - Opened by dkehlet over 4 years ago - 1 comment

#21 - Table 5 of AIB_Usage_Note_v1_2_2.pdf has errors in *adapter_rstn signal names

Issue - State: closed - Opened by dkehlet over 4 years ago - 1 comment

#20 - DFT ports modification. TCM hard coded to use functional clock only.

Pull Request - State: closed - Opened by xinyang2k over 4 years ago

#20 - DFT ports modification. TCM hard coded to use functional clock only.

Pull Request - State: closed - Opened by xinyang2k over 4 years ago

#19 - v2 slave needs to daisy-chain i_osc_clk

Issue - State: closed - Opened by dkehlet over 4 years ago - 1 comment

#19 - v2 slave needs to daisy-chain i_osc_clk

Issue - State: closed - Opened by dkehlet over 4 years ago - 1 comment

#18 - remove test clock. Clean lint check. Pull out m_fs_rcv_clk

Pull Request - State: closed - Opened by xinyang2k over 4 years ago

#18 - remove test clock. Clean lint check. Pull out m_fs_rcv_clk

Pull Request - State: closed - Opened by xinyang2k over 4 years ago

#17 - change DDR to SDR

Issue - State: closed - Opened by liuzixuan1212 over 4 years ago - 1 comment

#17 - change DDR to SDR

Issue - State: closed - Opened by liuzixuan1212 over 4 years ago - 1 comment

#16 - Added README.txt and sim_phasecom to rev2/dv/sims

Pull Request - State: closed - Opened by dkehlet over 4 years ago

#16 - Added README.txt and sim_phasecom to rev2/dv/sims

Pull Request - State: closed - Opened by dkehlet over 4 years ago

#15 - Added 2/2020 "Chiplets on the Rise" presentation

Pull Request - State: closed - Opened by dkehlet over 4 years ago

#15 - Added 2/2020 "Chiplets on the Rise" presentation

Pull Request - State: closed - Opened by dkehlet over 4 years ago

#14 - Updated AIB Usage Note

Pull Request - State: closed - Opened by dkehlet over 4 years ago

#14 - Updated AIB Usage Note

Pull Request - State: closed - Opened by dkehlet over 4 years ago

#13 - Typos in AIB specification 1.2

Issue - State: closed - Opened by dkehlet over 4 years ago - 1 comment

#12 - AIB 1.2 spec is missing Alternate (Slave) Channel Bump Map

Issue - State: closed - Opened by dkehlet over 4 years ago - 1 comment

#12 - AIB 1.2 spec is missing Alternate (Slave) Channel Bump Map

Issue - State: closed - Opened by dkehlet over 4 years ago - 1 comment

#11 - Bump spreadsheet is missing Slave interface locations

Issue - State: closed - Opened by dkehlet over 4 years ago - 1 comment

#11 - Bump spreadsheet is missing Slave interface locations

Issue - State: closed - Opened by dkehlet over 4 years ago - 1 comment

#10 - ms/sl_tx/rx_transfer_en ports pull out and modification for slave 2 a…

Pull Request - State: closed - Opened by xinyang2k almost 5 years ago

#10 - ms/sl_tx/rx_transfer_en ports pull out and modification for slave 2 a…

Pull Request - State: closed - Opened by xinyang2k almost 5 years ago

#9 - Synthesis of AIB

Issue - State: closed - Opened by rahulrvm82 almost 5 years ago - 1 comment

#9 - Synthesis of AIB

Issue - State: closed - Opened by rahulrvm82 almost 5 years ago - 1 comment

#8 - Port modification to add data_in_reg_mode and data_out_reg_mode to v2…

Pull Request - State: closed - Opened by xinyang2k almost 5 years ago

#8 - Port modification to add data_in_reg_mode and data_out_reg_mode to v2…

Pull Request - State: closed - Opened by xinyang2k almost 5 years ago

#7 - Modified slave 2 rtl update. Connection/loopback mode test fixing

Pull Request - State: closed - Opened by xinyang2k almost 5 years ago

#7 - Modified slave 2 rtl update. Connection/loopback mode test fixing

Pull Request - State: closed - Opened by xinyang2k almost 5 years ago

#6 - Modified slave 2 *dcc_dll_lock_req polarity from output to input

Pull Request - State: closed - Opened by xinyang2k almost 5 years ago

#6 - Modified slave 2 *dcc_dll_lock_req polarity from output to input

Pull Request - State: closed - Opened by xinyang2k almost 5 years ago

#4 - synthesis of the aib

Issue - State: closed - Opened by liuzixuan1212 almost 5 years ago - 7 comments

#3 - remove enhancement

Pull Request - State: closed - Opened by xinyang2k almost 5 years ago

#2 - remove enhancement

Pull Request - State: closed - Opened by xinyang2k almost 5 years ago

#1 - CHIPS Alliance spec

Pull Request - State: closed - Opened by dkehlet almost 5 years ago