Ecosyste.ms: Issues
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GitHub / chili-chips-ba/wireguard-fpga issues and pull requests
#11 - Add ability for interactive control of sim execution
Issue -
State: open - Opened by chili-chips-ba about 2 months ago
#10 - Creation of automated CSR test for RISC-V, based on RDL register definition
Issue -
State: open - Opened by chili-chips-ba about 2 months ago
Labels: discussion
#9 - 8 and 16-bit alignement of CSR fields in HAL
Issue -
State: open - Opened by chili-chips-ba about 2 months ago
- 3 comments
Labels: discussion
#8 - Tool version control and distribution: Central server, Docker, or Nix packages?!
Issue -
State: open - Opened by chili-chips-ba about 2 months ago
- 2 comments
Labels: discussion
#7 - Code Linting: RTL, CDC, C
Issue -
State: open - Opened by chili-chips-ba 2 months ago
Labels: discussion
#6 - Header Parser and IP Lookup function
Issue -
State: open - Opened by chili-chips-ba 2 months ago
- 1 comment
Labels: discussion
#5 - Misaligned Memory Access with GCC Optimizations (-O2) on RISC-V despite -mstrict-align
Issue -
State: open - Opened by tarik-ibrahimovic 2 months ago
- 20 comments
Labels: help wanted, question, SW
#4 - Co-sim/co-design with peakrdl output
Issue -
State: open - Opened by wyvernSemi 2 months ago
- 7 comments
Labels: discussion
#3 - Timing-aware ISS model
Issue -
State: open - Opened by chili-chips-ba 2 months ago
- 4 comments
Labels: discussion
#3 - Timing-aware ISS model
Issue -
State: open - Opened by chili-chips-ba 2 months ago
- 4 comments
Labels: discussion
#2 - Selection of the RISC-V CPU core for the project
Issue -
State: open - Opened by chili-chips-ba 2 months ago
- 10 comments
Labels: discussion
#1 - Stall-vs-Swap approach to atomic updates of large register banks, with fields wider than CPU bus
Issue -
State: open - Opened by chili-chips-ba 2 months ago
- 4 comments
Labels: discussion