Ecosyste.ms: Issues

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GitHub / cfelton/rhea issues and pull requests

#61 - register file example

Issue - State: open - Opened by hashhsah about 6 years ago

#60 - Renamed async to isasync

Pull Request - State: closed - Opened by aorcajo about 6 years ago - 2 comments

#60 - Renamed async to isasync

Pull Request - State: closed - Opened by aorcajo about 6 years ago - 2 comments

#59 - spi_slave_fifo_async

Issue - State: open - Opened by mngr0 over 6 years ago

#59 - spi_slave_fifo_async

Issue - State: open - Opened by mngr0 over 6 years ago

#58 - sdram controller

Issue - State: open - Opened by hstarmans about 8 years ago - 1 comment

#58 - sdram controller

Issue - State: open - Opened by hstarmans about 8 years ago - 1 comment

#57 - [enhancement] Provide board definition and blinky example for Red Pitaya

Issue - State: open - Opened by sanojb about 8 years ago - 1 comment

#56 - instructions: xula_blinky_host.py on raspberry pi 3B [solved]

Issue - State: open - Opened by hstarmans over 8 years ago - 7 comments

#53 - Symbol 'MMCME2_BASE' is not supported in target 'spartan6'.

Issue - State: open - Opened by NickShaffner over 8 years ago - 3 comments
Labels: enhancement

#52 - Fix for Issue #41 ISE 14.7 not handling escaped paths on windows 10

Pull Request - State: closed - Opened by NickShaffner over 8 years ago

#51 - ClockManagement's 'enable' parameter is not implemented on Xilinx parts

Issue - State: open - Opened by NickShaffner over 8 years ago - 2 comments
Labels: enhancement

#51 - ClockManagement's 'enable' parameter is not implemented on Xilinx parts

Issue - State: open - Opened by NickShaffner over 8 years ago - 2 comments
Labels: enhancement

#48 - Removing debug prints from xilinx clock management pll calculations.

Pull Request - State: closed - Opened by NickShaffner over 8 years ago - 3 comments

#48 - Removing debug prints from xilinx clock management pll calculations.

Pull Request - State: closed - Opened by NickShaffner over 8 years ago - 3 comments

#46 - The vivado path changes and vendor primitive fix.

Pull Request - State: closed - Opened by cfelton over 8 years ago - 1 comment

#46 - The vivado path changes and vendor primitive fix.

Pull Request - State: closed - Opened by cfelton over 8 years ago - 1 comment

#45 - [enhancement] create a skipif synthesis tool not available

Issue - State: open - Opened by cfelton over 8 years ago
Labels: enhancement

#45 - [enhancement] create a skipif synthesis tool not available

Issue - State: open - Opened by cfelton over 8 years ago
Labels: enhancement

#42 - Reworking docs for the rhea system

Pull Request - State: closed - Opened by FelixVi over 8 years ago - 4 comments

#42 - Reworking docs for the rhea system

Pull Request - State: closed - Opened by FelixVi over 8 years ago - 4 comments

#39 - Adding Numato Waxwing boards

Pull Request - State: closed - Opened by FelixVi over 8 years ago - 2 comments

#39 - Adding Numato Waxwing boards

Pull Request - State: closed - Opened by FelixVi over 8 years ago - 2 comments

#37 - Papilio Pro UART example

Pull Request - State: closed - Opened by FelixVi over 8 years ago - 3 comments

#37 - Papilio Pro UART example

Pull Request - State: closed - Opened by FelixVi over 8 years ago - 3 comments

#36 - A VGA timing fix and additional vga tests and examples.

Pull Request - State: closed - Opened by cfelton over 8 years ago - 1 comment

#36 - A VGA timing fix and additional vga tests and examples.

Pull Request - State: closed - Opened by cfelton over 8 years ago - 1 comment

#35 - vga: use the timing parameter class vs. function

Issue - State: open - Opened by cfelton over 8 years ago
Labels: enhancement

#33 - Additional port definitions for Digilent Anvyl

Pull Request - State: closed - Opened by NickShaffner over 8 years ago - 1 comment

#33 - Additional port definitions for Digilent Anvyl

Pull Request - State: closed - Opened by NickShaffner over 8 years ago - 1 comment

#32 - Papilio One board definition edits

Pull Request - State: closed - Opened by FelixVi over 8 years ago - 1 comment

#32 - Papilio One board definition edits

Pull Request - State: closed - Opened by FelixVi over 8 years ago - 1 comment

#31 - Added addtional port mappings to Digilent Anvyl board

Pull Request - State: closed - Opened by NickShaffner over 8 years ago - 8 comments

#31 - Added addtional port mappings to Digilent Anvyl board

Pull Request - State: closed - Opened by NickShaffner over 8 years ago - 8 comments

#30 - Papilio Pro board definitions

Pull Request - State: closed - Opened by FelixVi over 8 years ago - 2 comments

#29 - travis-ci build matrix

Issue - State: open - Opened by cfelton over 8 years ago
Labels: bug, help wanted

#29 - travis-ci build matrix

Issue - State: open - Opened by cfelton over 8 years ago
Labels: bug, help wanted

#28 - "Fixed Conversion Error"

Pull Request - State: closed - Opened by Vikram9866 almost 9 years ago - 7 comments

#27 - update README.md

Pull Request - State: closed - Opened by Vikram9866 almost 9 years ago

#27 - update README.md

Pull Request - State: closed - Opened by Vikram9866 almost 9 years ago

#26 - Addition of the Altera DE1 SOC board definition and basic examples.

Pull Request - State: closed - Opened by Godtec almost 9 years ago - 3 comments

#26 - Addition of the Altera DE1 SOC board definition and basic examples.

Pull Request - State: closed - Opened by Godtec almost 9 years ago - 3 comments

#25 - DE1_Soc Pull request

Pull Request - State: closed - Opened by Godtec almost 9 years ago - 7 comments

#25 - DE1_Soc Pull request

Pull Request - State: closed - Opened by Godtec almost 9 years ago - 7 comments

#24 - Change GPIO pin assignments to Peripheral based devices vs FPGA based.

Issue - State: closed - Opened by Godtec almost 9 years ago - 6 comments

#24 - Change GPIO pin assignments to Peripheral based devices vs FPGA based.

Issue - State: closed - Opened by Godtec almost 9 years ago - 6 comments

#23 - Add a digilent basys3 board definition

Issue - State: open - Opened by cfelton almost 9 years ago
Labels: enhancement, help wanted

#22 - added support for De1-SoC Terasic FPGA Board.

Pull Request - State: closed - Opened by Godtec almost 9 years ago - 1 comment

#22 - added support for De1-SoC Terasic FPGA Board.

Pull Request - State: closed - Opened by Godtec almost 9 years ago - 1 comment

#21 - typo

Pull Request - State: closed - Opened by hstarmans almost 9 years ago - 1 comment

#21 - typo

Pull Request - State: closed - Opened by hstarmans almost 9 years ago - 1 comment

#20 - Marked slow running tests to skip in py.test

Pull Request - State: closed - Opened by gcc42 almost 9 years ago - 9 comments

#20 - Marked slow running tests to skip in py.test

Pull Request - State: closed - Opened by gcc42 almost 9 years ago - 9 comments

#19 - Outside Interfacing

Issue - State: closed - Opened by zignig almost 9 years ago - 1 comment

#19 - Outside Interfacing

Issue - State: closed - Opened by zignig almost 9 years ago - 1 comment

#18 - typo

Pull Request - State: closed - Opened by zignig almost 9 years ago - 3 comments

#18 - typo

Pull Request - State: closed - Opened by zignig almost 9 years ago - 3 comments

#17 - Long simulation tests

Issue - State: closed - Opened by cfelton almost 9 years ago - 2 comments

#16 - fix test_emesh_fifo test

Issue - State: open - Opened by cfelton almost 9 years ago
Labels: bug

#16 - fix test_emesh_fifo test

Issue - State: open - Opened by cfelton almost 9 years ago
Labels: bug

#15 - Replacing register-file definitions with control-status-objects (cso)

Pull Request - State: closed - Opened by cfelton almost 9 years ago

#15 - Replacing register-file definitions with control-status-objects (cso)

Pull Request - State: closed - Opened by cfelton almost 9 years ago

#14 - Added more tests for fifo_fast

Pull Request - State: closed - Opened by gcc42 almost 9 years ago - 5 comments

#14 - Added more tests for fifo_fast

Pull Request - State: closed - Opened by gcc42 almost 9 years ago - 5 comments

#13 - Complete the fifo tests

Issue - State: closed - Opened by cfelton almost 9 years ago - 1 comment
Labels: help wanted

#13 - Complete the fifo tests

Issue - State: closed - Opened by cfelton almost 9 years ago - 1 comment
Labels: help wanted

#12 - Changed uart to use a single external fifobus interface

Pull Request - State: closed - Opened by gcc42 almost 9 years ago - 6 comments

#12 - Changed uart to use a single external fifobus interface

Pull Request - State: closed - Opened by gcc42 almost 9 years ago - 6 comments

#11 - Renamed the attributes in the system/stream/FIFOBus interface.

Pull Request - State: closed - Opened by gcc42 almost 9 years ago - 4 comments

#11 - Renamed the attributes in the system/stream/FIFOBus interface.

Pull Request - State: closed - Opened by gcc42 almost 9 years ago - 4 comments

#10 - Rename the attributes in the FIFOBus interface

Issue - State: closed - Opened by cfelton almost 9 years ago - 1 comment
Labels: help wanted

#9 - UART lite modifications

Issue - State: closed - Opened by cfelton almost 9 years ago - 1 comment
Labels: help wanted

#8 - Patch for #7, cleanup fifo_syncers

Pull Request - State: closed - Opened by meetps about 9 years ago

#7 - fifo_syncers cleanup

Issue - State: closed - Opened by cfelton about 9 years ago
Labels: help wanted

#6 - Docbug: PULLUP='PULLUP' doesn't work.

Pull Request - State: closed - Opened by gbin about 9 years ago - 1 comment

#5 - Can't make blinky work on Mojo v3.

Issue - State: closed - Opened by gbin about 9 years ago - 5 comments
Labels: enhancement

#4 - RFC Tidy test pins

Pull Request - State: closed - Opened by robtaylor over 9 years ago - 4 comments

#3 - De0 cv and python 3 fixes

Pull Request - State: closed - Opened by robtaylor over 9 years ago

#2 - Check that the "tools" are accessible before running

Issue - State: closed - Opened by cfelton over 9 years ago - 1 comment