Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / byuccl/spydrnet issues and pull requests

#223 - Added default_nettype as a verilog token

Pull Request - State: closed - Opened by ganeshgore 5 months ago

#222 - is_downto flag fix for big-endian bundle declaration

Pull Request - State: closed - Opened by ganeshgore 5 months ago

#221 - Incorrect handling of big-endian declaration (is_downto=false)

Issue - State: closed - Opened by ganeshgore 5 months ago - 5 comments
Labels: resolved?

#220 - Flatten cannot handle multiple instances of one definition in another definition.

Issue - State: open - Opened by zhuguiyuan 5 months ago - 2 comments
Labels: documentation

#219 - Fix version string on non-master branch to comply with PEP440

Pull Request - State: closed - Opened by jgoeders 9 months ago

#217 - Add python 3.11 to CI

Pull Request - State: closed - Opened by jgoeders 9 months ago

#216 - `\<const0>` and `\<const1>` missing drivers

Issue - State: closed - Opened by jgoeders 9 months ago - 3 comments
Labels: resolved?

#215 - EDIF files generated by Atmel CPLD fitter unparsable.

Issue - State: open - Opened by peterzieba 9 months ago - 11 comments
Labels: resolved?

#214 - Verilog: Support concatenation in assign statements

Issue - State: closed - Opened by jacobdbrown4 9 months ago - 1 comment

#213 - Getting recursion error when parsing a netlist

Issue - State: open - Opened by arun-chaubey 9 months ago - 7 comments
Labels: resolved?

#212 - `requests` package dependency not in setup.py

Issue - State: closed - Opened by jgoeders 10 months ago - 2 comments
Labels: resolved?

#211 - Handle(again) params in module's body and multi-entry assigns in Verilog parser

Pull Request - State: closed - Opened by Chopper455 10 months ago - 5 comments

#208 - SpyDrNet 1.13.0

Pull Request - State: closed - Opened by jacobdbrown4 10 months ago

#207 - Create CoLab examples

Issue - State: open - Opened by wirthlin about 1 year ago
Labels: documentation

#206 - Move Tests Out of the Package

Issue - State: closed - Opened by jacobdbrown4 about 1 year ago - 5 comments

#205 - SpyDrNet 1.12.2

Pull Request - State: closed - Opened by emonlux about 1 year ago

#204 - SpyDrNet 1.12.2

Pull Request - State: closed - Opened by emonlux about 1 year ago

#203 - Include type hinting

Issue - State: open - Opened by agg23 over 1 year ago - 1 comment

#202 - Handling Intel architecture definitions

Issue - State: open - Opened by agg23 over 1 year ago - 1 comment

#201 - [verilog] Primitives

Issue - State: open - Opened by agg23 over 1 year ago - 4 comments

#200 - Zipped support files

Issue - State: closed - Opened by agg23 over 1 year ago - 6 comments

#199 - [verilog] Fixed parser not properly handling empty instance port list

Pull Request - State: closed - Opened by agg23 over 1 year ago

#198 - Wrong pin indexing on partially connected output port

Issue - State: closed - Opened by jgoeders over 1 year ago - 5 comments

#197 - Instance names have space at the end

Issue - State: closed - Opened by jgoeders over 1 year ago - 4 comments

#196 - Distinguishing pins in multi-bit ports

Issue - State: open - Opened by jgoeders over 1 year ago - 5 comments
Labels: resolved?

#195 - parse should work with Pathlib.Path

Issue - State: closed - Opened by jgoeders over 1 year ago - 10 comments

#194 - SpyDrNet 1.12.1

Pull Request - State: closed - Opened by jacobdbrown4 over 1 year ago

#193 - SpyDrNet 1.12.0

Pull Request - State: closed - Opened by jacobdbrown4 over 1 year ago

#192 - Delete Old Branches

Issue - State: open - Opened by jacobdbrown4 over 1 year ago - 5 comments

#191 - Transformation to and from EBLIF

Issue - State: open - Opened by emonlux almost 2 years ago - 1 comment

#190 - Added sort all flag to the Verilog composer

Pull Request - State: closed - Opened by ganeshgore almost 2 years ago - 3 comments

#189 - Composer skip constraints

Pull Request - State: closed - Opened by ganeshgore almost 2 years ago - 1 comment

#188 - [Bugfix] constant net name

Pull Request - State: closed - Opened by ganeshgore almost 2 years ago - 1 comment

#187 - Strict code formatting

Issue - State: closed - Opened by ganeshgore almost 2 years ago - 5 comments

#186 - Added pytest for multiple wire declaration

Pull Request - State: closed - Opened by ganeshgore almost 2 years ago - 1 comment

#185 - Make SpyDrNet internals completely generic

Issue - State: open - Opened by jacobdbrown4 almost 2 years ago - 2 comments

#184 - Verilog Composer Writing Module Header Port Concatenations

Issue - State: closed - Opened by jacobdbrown4 almost 2 years ago - 2 comments

#183 - Issues parsing F4PGA-generated reverse-netlists.

Issue - State: closed - Opened by JakeEdvenson almost 2 years ago - 2 comments

#182 - Case Sensitivity - EDIF composer

Issue - State: open - Opened by emonlux about 2 years ago - 10 comments

#181 - Verilog parser not parsing file

Issue - State: closed - Opened by emonlux about 2 years ago - 2 comments

#180 - Hierarchy Support in BLIF/EBLIF

Issue - State: closed - Opened by jacobdbrown4 about 2 years ago - 1 comment

#179 - Built-In Primitive Library FPGA Architecture libraries

Issue - State: closed - Opened by jacobdbrown4 about 2 years ago - 3 comments

#178 - Setting correct top module when parsing netlist from Lattice

Issue - State: open - Opened by jacobdbrown4 about 2 years ago - 4 comments
Labels: resolved?

#177 - Verilog parsing fails when ports implicitly mapped

Issue - State: closed - Opened by jacobdbrown4 about 2 years ago - 1 comment

#176 - Initial support for case insensitive naming

Pull Request - State: closed - Opened by slide about 2 years ago - 5 comments

#175 - SpyDrNet 1.11.1

Pull Request - State: closed - Opened by jacobdbrown4 about 2 years ago

#174 - EBLIF parser and composer not included in 1.11.0 python packages

Issue - State: closed - Opened by jacobdbrown4 about 2 years ago - 1 comment

#173 - Example netlists of formats other than EDIF

Issue - State: closed - Opened by jacobdbrown4 about 2 years ago - 2 comments

#172 - SpyDrNet 1.11.0

Pull Request - State: closed - Opened by jacobdbrown4 about 2 years ago

#171 - SpyDrNet 1.10.1

Pull Request - State: closed - Opened by jacobdbrown4 over 2 years ago

#170 - v.1.10.0

Pull Request - State: closed - Opened by jacobdbrown4 over 2 years ago

#169 - Basic Pytest to tests extension loading and extended methods

Pull Request - State: closed - Opened by ganeshgore over 2 years ago

#168 - SpyDrNet Extensions [ PR 3/3 ] - Updated spydrnet.ir.__init__ file

Pull Request - State: closed - Opened by ganeshgore over 2 years ago - 6 comments

#167 - SpyDrNet Extensions [ PR 2/3 ] - Updated ir classes import path

Pull Request - State: closed - Opened by ganeshgore over 2 years ago - 2 comments

#166 - SpyDrNet Extensions [ PR 1/3 ] - Added extension discovery and logger

Pull Request - State: closed - Opened by ganeshgore over 2 years ago - 6 comments

#165 - v1.9.0

Pull Request - State: closed - Opened by jacobdbrown4 over 2 years ago

#164 - Installation issue: pip install -e .

Issue - State: closed - Opened by wirthlin over 2 years ago - 2 comments

#163 - Make the EDIF tokenizer support strings that contain the % sign

Pull Request - State: closed - Opened by chgentso over 2 years ago - 1 comment

#162 - HTML Composer 1 - IR changes

Pull Request - State: open - Opened by ganeshgore over 2 years ago - 5 comments

#161 - Enhancing verilog composer

Pull Request - State: closed - Opened by ganeshgore over 2 years ago - 5 comments

#160 - Extending SpyDrNet classes to implement application specific package

Issue - State: closed - Opened by ganeshgore over 2 years ago - 20 comments

#159 - Create pins and wires during port and cable addition in definition

Pull Request - State: closed - Opened by ganeshgore over 2 years ago - 3 comments

#158 - Changed comment handling in Verilog Tokenizer

Pull Request - State: closed - Opened by ganeshgore over 2 years ago - 3 comments

#157 - Adding GitHub actions for CI regression

Pull Request - State: closed - Opened by ganeshgore over 2 years ago - 1 comment

#156 - Comments at the end of the Verilog code break the Verilog Parser

Issue - State: closed - Opened by ganeshgore over 2 years ago - 3 comments

#155 - Can you store an instance's information in an HRef object?

Issue - State: open - Opened by jacobdbrown4 over 2 years ago - 9 comments
Labels: resolved?

#154 - Support Lattice Semiconductor netlists (Verilog based)

Issue - State: closed - Opened by wirthlin almost 3 years ago - 1 comment
Labels: minor

#153 - Not all example netlists working

Issue - State: closed - Opened by benglines almost 3 years ago - 5 comments

#152 - is_top_instance attribute for instances

Issue - State: closed - Opened by jacobdbrown4 almost 3 years ago

#151 - EDIF parser pytest coverage

Issue - State: open - Opened by jacobdbrown4 almost 3 years ago

#150 - Document pylint log before each release

Issue - State: closed - Opened by jacobdbrown4 almost 3 years ago - 3 comments

#149 - v1.8.3

Pull Request - State: closed - Opened by jacobdbrown4 almost 3 years ago

#148 - Incorrect multi bit cables after EDIF parser

Issue - State: closed - Opened by jacobdbrown4 almost 3 years ago - 9 comments

#147 - Parse .edn files

Issue - State: closed - Opened by wirthlin almost 3 years ago - 1 comment

#146 - v.1.8.2

Pull Request - State: closed - Opened by jacobdbrown4 about 3 years ago

#144 - Create Xilinx library

Issue - State: open - Opened by wirthlin about 3 years ago - 5 comments
Labels: minor

#142 - Clean up the namespace managers' implementations

Issue - State: open - Opened by thunder-hammer about 3 years ago - 2 comments

#141 - Verilog Parser features required to parse Quartus Prime .vo/vqm files

Issue - State: open - Opened by thunder-hammer about 3 years ago - 4 comments

#140 - Analyze and improve constant support Verilog Parser

Issue - State: open - Opened by thunder-hammer about 3 years ago

#139 - instance.get_pins() vs instance.pins

Issue - State: open - Opened by jacobdbrown4 about 3 years ago - 6 comments
Labels: major

#138 - Documentation about building the documentation

Issue - State: open - Opened by thunder-hammer about 3 years ago

#137 - Next release

Pull Request - State: closed - Opened by jordi1215 about 3 years ago

#136 - Need to document the examples

Issue - State: open - Opened by wirthlin about 3 years ago - 1 comment
Labels: good first issue

#135 - Verilog Parser and composer improvements.

Pull Request - State: closed - Opened by thunder-hammer about 3 years ago

#134 - Add a script to the build documentation

Issue - State: closed - Opened by thunder-hammer about 3 years ago - 1 comment

#133 - Version Display

Issue - State: closed - Opened by benglines about 3 years ago - 2 comments
Labels: documentation

#132 - Verilog Composer improvements needed

Issue - State: closed - Opened by thunder-hammer about 3 years ago - 2 comments

#131 - Delete test.py

Pull Request - State: closed - Opened by jordi1215 about 3 years ago - 1 comment

#130 - Additional visualization example file

Issue - State: open - Opened by thunder-hammer about 3 years ago - 6 comments

#129 - Add some additional information to the documentation

Issue - State: open - Opened by thunder-hammer about 3 years ago - 2 comments
Labels: documentation, good first issue

#126 - Additional Testing needed.

Issue - State: closed - Opened by thunder-hammer over 3 years ago - 4 comments

#123 - Verilog to edif

Pull Request - State: closed - Opened by thunder-hammer over 3 years ago

#107 - Documentation improvements and clarifications

Issue - State: open - Opened by thunder-hammer about 4 years ago - 1 comment
Labels: documentation, size 5

#106 - WIP: Issue#79

Pull Request - State: closed - Opened by thunder-hammer about 4 years ago

#105 - Tutorial into the documentation

Issue - State: closed - Opened by thunder-hammer about 4 years ago - 5 comments
Labels: documentation, enhancement, size 3