Ecosyste.ms: Issues

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GitHub / benreynwar/axilent issues and pull requests

#10 - Compare with Xilinx's PYNQ

Issue - State: open - Opened by benreynwar about 6 years ago

#9 - Reproducible FPGA simulations

Issue - State: open - Opened by benreynwar about 6 years ago

#8 - Add fusesoc handler

Issue - State: open - Opened by benreynwar about 6 years ago

#7 - Add PYNQ handler

Issue - State: open - Opened by benreynwar about 6 years ago

#6 - Add verilator handler

Issue - State: open - Opened by benreynwar about 6 years ago

#5 - Add cocotb handler

Issue - State: open - Opened by benreynwar about 6 years ago

#4 - Add Verilog support

Issue - State: closed - Opened by mithro about 6 years ago - 1 comment

#3 - Enable readthedocs.io and add documentation :-)

Issue - State: open - Opened by mithro about 6 years ago - 1 comment

#2 - Add a LICENSE file to this

Issue - State: closed - Opened by mithro about 6 years ago - 1 comment

#1 - Multi clocks

Pull Request - State: closed - Opened by benreynwar about 6 years ago