Ecosyste.ms: Issues

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GitHub / barrettotte/subarashii-cpu issues and pull requests

#29 - Phase 2 planning and design

Issue - State: closed - Opened by barrettotte almost 6 years ago

#29 - Phase 2 planning and design

Issue - State: closed - Opened by barrettotte almost 6 years ago

#28 - ALU ADD/SUB operations (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#28 - ALU ADD/SUB operations (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#27 - Breadboard implementation of ALU

Issue - State: closed - Opened by barrettotte almost 6 years ago

#27 - Breadboard implementation of ALU

Issue - State: closed - Opened by barrettotte almost 6 years ago

#26 - VHDL implementation of ALU

Issue - State: closed - Opened by barrettotte almost 6 years ago

#26 - VHDL implementation of ALU

Issue - State: closed - Opened by barrettotte almost 6 years ago

#25 - Make an emulator in Python or C++

Issue - State: closed - Opened by barrettotte almost 6 years ago

#25 - Make an emulator in Python or C++

Issue - State: closed - Opened by barrettotte almost 6 years ago

#24 - Finish up phase 1 implementation and documentation

Issue - State: closed - Opened by barrettotte almost 6 years ago

#24 - Finish up phase 1 implementation and documentation

Issue - State: closed - Opened by barrettotte almost 6 years ago

#23 - Make register bank (VHDL)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#23 - Make register bank (VHDL)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#22 - Finish phase 1 VHDL implementation

Issue - State: closed - Opened by barrettotte almost 6 years ago

#22 - Finish phase 1 VHDL implementation

Issue - State: closed - Opened by barrettotte almost 6 years ago

#21 - Test register bank (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#21 - Test register bank (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#20 - Implement Rd selector (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#20 - Implement Rd selector (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#19 - LEDs for registers and register selectors

Issue - State: closed - Opened by barrettotte almost 6 years ago

#19 - LEDs for registers and register selectors

Issue - State: closed - Opened by barrettotte almost 6 years ago

#18 - Test all phase 1 VHDL

Issue - State: closed - Opened by barrettotte almost 6 years ago

#18 - Test all phase 1 VHDL

Issue - State: closed - Opened by barrettotte almost 6 years ago

#17 - Implement Rs selector (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#17 - Implement Rs selector (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#16 - Replace registers with new compact design

Issue - State: closed - Opened by barrettotte almost 6 years ago

#16 - Replace registers with new compact design

Issue - State: closed - Opened by barrettotte almost 6 years ago

#15 - Rewrite VHDL implementation in terms of IC's

Issue - State: closed - Opened by barrettotte almost 6 years ago

#15 - Rewrite VHDL implementation in terms of IC's

Issue - State: closed - Opened by barrettotte almost 6 years ago

#14 - Make block diagrams for ALU, clock, and register bank

Issue - State: closed - Opened by barrettotte almost 6 years ago

#14 - Make block diagrams for ALU, clock, and register bank

Issue - State: closed - Opened by barrettotte almost 6 years ago

#12 - Make last four 8-bit registers (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#12 - Make last four 8-bit registers (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#11 - Design ALU

Issue - State: closed - Opened by barrettotte almost 6 years ago

#11 - Design ALU

Issue - State: closed - Opened by barrettotte almost 6 years ago

#10 - Make four 8-bit registers (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#10 - Make four 8-bit registers (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#9 - Design RISC instruction set

Issue - State: closed - Opened by barrettotte almost 6 years ago

#9 - Design RISC instruction set

Issue - State: closed - Opened by barrettotte almost 6 years ago

#8 - Begin documentation and design ISA

Issue - State: closed - Opened by barrettotte almost 6 years ago

#8 - Begin documentation and design ISA

Issue - State: closed - Opened by barrettotte almost 6 years ago

#7 - Implement an 8-bit register (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#7 - Implement an 8-bit register (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#6 - Plan out phase 1 goals

Issue - State: closed - Opened by barrettotte almost 6 years ago

#5 - Make clock module (astable/bistable) (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#4 - Research and decide on CPU architecture to implement

Issue - State: closed - Opened by barrettotte almost 6 years ago

#3 - Wire Rs and Rd to temp bus for phase 2 (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#2 - Wire data bus to registers A-H (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago

#1 - Make register bank (breadboard)

Issue - State: closed - Opened by barrettotte almost 6 years ago