Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / aws/aws-fpga issues and pull requests

#582 - trivial update

Pull Request - State: closed - Opened by kyyalama2 over 2 years ago

#581 - [Question]: FPGA Peer2Peer Build Process

Issue - State: closed - Opened by sajjadahmed677 over 2 years ago - 4 comments

#580 - Remove git clean invocation from DRAM model generation

Pull Request - State: closed - Opened by davidbiancolin over 2 years ago - 6 comments

#579 - Xilinx 2022.1

Issue - State: closed - Opened by bjourne over 2 years ago - 19 comments

#578 - What is the reason for reset synchronization in new CL design template?

Issue - State: closed - Opened by za1nrkhan over 2 years ago - 1 comment

#577 - What is xdma0_user mapped to?

Issue - State: closed - Opened by Quarky93 over 2 years ago - 3 comments

#576 - Updates to documentation

Pull Request - State: closed - Opened by kyyalama2 over 2 years ago

#575 - Does HLX flow still work?

Issue - State: closed - Opened by Quarky93 over 2 years ago - 11 comments

#574 - Unable to run FPGA dev AMI on r6 and c6 instances

Issue - State: closed - Opened by kenta2 over 2 years ago - 3 comments

#573 - Example cl_hello_world_ref_hlx fails in newer Vivado versions

Issue - State: closed - Opened by wirthjohannes over 2 years ago - 6 comments

#572 - Using-PCIe-Write-Combining example returns unexpected results

Issue - State: open - Opened by itamarblum over 2 years ago - 3 comments

#571 - Unable to run FPGA dev AMI on m6a or m6i instances

Issue - State: closed - Opened by kenta2 over 2 years ago - 6 comments

#570 - XOCL installation failed.

Issue - State: closed - Opened by Shahzaib2028 over 2 years ago - 2 comments

#569 - Fixed the cl_uram_example Constraints

Pull Request - State: closed - Opened by kyyalama2 over 2 years ago

#568 - Update wait_for_afi.md

Pull Request - State: closed - Opened by kyyalama2 over 2 years ago

#567 - fix broken links in the RTL_sim doc (#715)

Pull Request - State: closed - Opened by kyyalama2 over 2 years ago

#566 - pnr updates for uram fix

Pull Request - State: closed - Opened by kyyalama2 over 2 years ago

#565 - [Quesstion]: Simulation of virtual jtag facility

Issue - State: closed - Opened by sajjadahmed677 over 2 years ago - 7 comments

#564 - non-default device IDs and udev rules

Issue - State: closed - Opened by jacobmgn over 2 years ago

#561 - fixes #560: udev rule not running after loading fpga image

Pull Request - State: closed - Opened by cmoore1776 over 2 years ago - 1 comment

#560 - udev rule not running after loading fpga image

Issue - State: open - Opened by cmoore1776 over 2 years ago - 6 comments

#559 - prepare_new_cl.sh generates broken scripts and templates.

Issue - State: open - Opened by jahagirdar over 2 years ago - 4 comments

#558 - Notify scripts gives boto3.exception

Issue - State: closed - Opened by jahagirdar over 2 years ago - 6 comments

#556 - AXI "bvalid" behavior and latency

Issue - State: closed - Opened by useragdp1 almost 3 years ago - 3 comments

#555 - Some image URLs are broken in documentation

Issue - State: closed - Opened by whentojump almost 3 years ago - 3 comments

#554 - [Question]: DDR Burst Read

Issue - State: closed - Opened by sajjadahmed677 almost 3 years ago - 4 comments

#543 - can't find xilinx_aws-vu9p-f1-04261818_dynamic_5_0.dsa file in aws_platform

Issue - State: closed - Opened by umairqaisar000 about 3 years ago - 6 comments

#542 - Running Hardware development kit in AWS FPGA development and s3 bucket creation

Issue - State: closed - Opened by SSandeep19 about 3 years ago - 2 comments

#513 - source sdaccel_setup.sh on FPGA DEV AMI

Issue - State: closed - Opened by mcousine almost 4 years ago - 3 comments

#508 - XILINX_VITIS varaiblet not set

Issue - State: closed - Opened by yanyr over 4 years ago - 6 comments