Ecosyste.ms: Issues

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GitHub / alexforencich/verilog-lfsr issues and pull requests

#5 - Fix post-synthesis simulation in yosys

Pull Request - State: open - Opened by Forty-Bot about 2 years ago - 7 comments

#4 - Working in simulation but incorrect synthesis output?

Issue - State: open - Opened by bretthannigan almost 4 years ago - 4 comments

#3 - How can i use the lfsr in parallel mode?

Issue - State: closed - Opened by Jzone315 over 5 years ago - 8 comments
Labels: question

#1 - How to use it in ethernet 32-bits?

Issue - State: closed - Opened by Jzone315 over 6 years ago - 7 comments