alexforencich/verilog-ethernet issues and pull requests

#45 - Making of Example Vivado Project

Issue - State: closed - Opened by FPGA-Bot-Yang over 4 years ago - 7 comments

#44 - DE2115 TXD

Issue - State: closed - Opened by nitya261 over 4 years ago - 1 comment

#43 - missing parts for PTP and 1g example design with PTP source

Issue - State: closed - Opened by gruberth96 over 4 years ago - 6 comments

#42 - Arty test, can't see loopback message

Issue - State: closed - Opened by kimanha over 4 years ago - 17 comments

#41 - AU50 and AU280 build error

Issue - State: closed - Opened by kimanha over 4 years ago - 3 comments

#40 - Is there any example for UDP stack + DHCP?

Issue - State: open - Opened by qrp73 over 4 years ago - 2 comments

#39 - ENABLE_PADDING(0) leads to failure

Issue - State: closed - Opened by qrp73 over 4 years ago - 4 comments

#38 - make error at Cygwin64

Issue - State: closed - Opened by kimanha over 4 years ago - 1 comment

#37 - Problem with sythesizing - VCU108 - fpga_1g

Issue - State: closed - Opened by seva-r over 4 years ago - 3 comments

#36 - Which NIC did you use for the AU50 example?

Issue - State: closed - Opened by TaekyungHeo over 4 years ago - 4 comments

#35 - PC Ethernet connection settings

Issue - State: closed - Opened by bashidagha over 4 years ago - 11 comments

#34 - Vivado block diagram, recursive priority encoder

Issue - State: open - Opened by Neywiny over 4 years ago - 8 comments

#33 - Bypass Xilinx PCS?

Issue - State: open - Opened by billmacdowell over 4 years ago - 1 comment
Labels: question

#32 - Undriven PTP inputs when instancing 'eth_mac_1g'

Issue - State: closed - Opened by egrigor over 4 years ago - 30 comments

#31 - make build error for VCU118 projects

Issue - State: closed - Opened by wrmarchetto almost 5 years ago - 2 comments
Labels: question

#30 - VCU-118 10G and 25G Ethernet half expected data rate

Issue - State: open - Opened by MostParsingVex almost 5 years ago - 2 comments
Labels: question

#29 - RX_DROP_BAD_FRAME in eth_mac_1g_fifo.v

Issue - State: closed - Opened by eugene-tarassov almost 5 years ago - 1 comment

#28 - VCU118 25G ...payload_axis_tdata[] width

Issue - State: closed - Opened by MostParsingVex almost 5 years ago - 2 comments

#27 - Minor fixes and improvements

Pull Request - State: open - Opened by Reisswolf almost 5 years ago

#26 - Converted local parameter definitions & Added missing ports in module instances

Pull Request - State: closed - Opened by Reisswolf almost 5 years ago - 9 comments

#25 - rd_hash & wr_hash module not found

Issue - State: closed - Opened by hushunkui almost 5 years ago - 1 comment
Labels: question

#24 - Block Diagram

Issue - State: closed - Opened by pfrankis almost 5 years ago - 2 comments

#23 - UDP invalid payload length

Issue - State: closed - Opened by DeadMaX almost 5 years ago - 2 comments

#22 - The sample udp loopback respond to other IP

Issue - State: open - Opened by DeadMaX almost 5 years ago

#21 - Script to run all the test cases in tb folder

Pull Request - State: closed - Opened by LeChuck42 almost 5 years ago - 2 comments

#20 - Recursive call in priority encoder doesn't seem to work in Synplify

Issue - State: closed - Opened by chen-m76 about 5 years ago - 6 comments

#19 - gig_ethernet_pcs_pma_0 IP on board VCU108 (1g example)

Issue - State: closed - Opened by ranjanbl about 5 years ago - 2 comments

#18 - ARP: resolve IP multicast

Pull Request - State: open - Opened by sergachev about 5 years ago - 3 comments

#17 - Problems trying to combine GMII MAC Module with Xilinx PCS/PMA IP

Issue - State: closed - Opened by KevinSmild over 5 years ago - 8 comments
Labels: question

#16 - porting to a ZCU102 and ZCU111?

Issue - State: open - Opened by sirjansel0t over 5 years ago - 18 comments
Labels: question

#15 - axis_xgmii_tx_32 state_reg not big enough

Issue - State: closed - Opened by philn16 over 5 years ago - 1 comment

#14 - A complete Quartus Prime 17.1 project (Windows)

Pull Request - State: open - Opened by briansune over 5 years ago

#13 - Use of tkeep in the middle of a packet for ignoring bytes

Issue - State: closed - Opened by olagrottvik over 5 years ago - 3 comments
Labels: question

#12 - Unconnected clear_cache in arp_cache.v

Issue - State: closed - Opened by olagrottvik over 5 years ago - 6 comments
Labels: bug, enhancement

#11 - udp_complete for tx only

Issue - State: open - Opened by olagrottvik almost 6 years ago - 8 comments
Labels: enhancement, question

#10 - Any documents on how to use UDP stack?

Issue - State: closed - Opened by sinaaghli almost 6 years ago - 12 comments
Labels: question

#9 - How to apply your project into ZC706?

Issue - State: open - Opened by JackieLee0524 almost 6 years ago - 4 comments
Labels: question

#8 - Fixed the size of data_reg nets

Pull Request - State: closed - Opened by pdabholkar almost 6 years ago - 1 comment

#7 - First byte of Ethernet preamble being replaced by XGMII start byte

Issue - State: closed - Opened by philn16 about 6 years ago - 3 comments

#6 - Genesys2

Pull Request - State: open - Opened by jrrk about 6 years ago

#5 - ML605 example

Issue - State: closed - Opened by themperek almost 7 years ago - 3 comments

#4 - eth_crc_8.v missing

Issue - State: closed - Opened by kabaka0 over 7 years ago - 4 comments

#3 - Typo in eth_gth_phy_quad.v line 233

Issue - State: closed - Opened by CodeWarrior1241 almost 9 years ago - 1 comment

#2 - Signal disable_drp_mgmt undeclared in eth_gth_phy_quad.v

Issue - State: closed - Opened by CodeWarrior1241 about 9 years ago - 2 comments

#1 - Using 10GbE UDP for ZC706 board

Issue - State: closed - Opened by CodeWarrior1241 about 9 years ago - 1 comment

GitHub / alexforencich/verilog-ethernet issues and pull requests