alexforencich/verilog-ethernet issues and pull requests

#229 - export to ku060

Issue - State: open - Opened by andylgh about 2 months ago - 7 comments

#228 - No rule to make target

Issue - State: open - Opened by pitpg about 2 months ago

#227 - Update axis_xgmii_tx_64.v

Pull Request - State: open - Opened by drewranck about 2 months ago

#226 - Wrong bit with on 10G MAC Tx start_packet_reg

Issue - State: open - Opened by drewranck about 2 months ago

#225 - multiple UDP stream support

Issue - State: open - Opened by lizajoseph 2 months ago

#224 - ADM-PCIE-9V3 example not working

Issue - State: closed - Opened by harris-chris 2 months ago - 4 comments

#102 - Can't send two or more consecutive frames

Issue - State: closed - Opened by GiovanniCmpaner almost 3 years ago

#101 - there is no TCP module

Issue - State: closed - Opened by wangce888 about 3 years ago

#100 - Link detection is failed

Issue - State: closed - Opened by minlno about 3 years ago

#100 - Link detection is failed

Issue - State: closed - Opened by minlno about 3 years ago

#99 - Question about ASYNC_REG

Issue - State: open - Opened by Yuan-Mao about 3 years ago - 6 comments

#99 - Question about ASYNC_REG

Issue - State: open - Opened by Yuan-Mao about 3 years ago - 6 comments

#98 - Linux Device Driver Support

Issue - State: open - Opened by Yuan-Mao about 3 years ago - 9 comments

#98 - Linux Device Driver Support

Issue - State: open - Opened by Yuan-Mao about 3 years ago - 9 comments

#97 - eth_mac_1g bad frame error

Issue - State: closed - Opened by cws11 about 3 years ago - 2 comments

#97 - eth_mac_1g bad frame error

Issue - State: closed - Opened by cws11 about 3 years ago - 2 comments

#96 - Add Xilinx Kintex UltraScale+ KCU116 board

Pull Request - State: open - Opened by lschuermann about 3 years ago

#96 - Add Xilinx Kintex UltraScale+ KCU116 board

Pull Request - State: open - Opened by lschuermann about 3 years ago

#95 - ASIC implementation for verilog-ethernet

Issue - State: open - Opened by Yuan-Mao about 3 years ago - 5 comments

#95 - ASIC implementation for verilog-ethernet

Issue - State: open - Opened by Yuan-Mao about 3 years ago - 5 comments

#94 - Sending large UDP packets

Issue - State: closed - Opened by IvanSavelyev about 3 years ago - 2 comments

#93 - Example for Digilent Genesys2 board (XC7K325T)

Pull Request - State: open - Opened by unbtorsten about 3 years ago

#93 - Example for Digilent Genesys2 board (XC7K325T)

Pull Request - State: open - Opened by unbtorsten about 3 years ago

#92 - VLAN support

Issue - State: open - Opened by thienanvu about 3 years ago - 4 comments

#92 - VLAN support

Issue - State: open - Opened by thienanvu about 3 years ago - 4 comments

#91 - VCU118 problem

Issue - State: closed - Opened by jalilisahar about 3 years ago - 1 comment

#91 - VCU118 problem

Issue - State: closed - Opened by jalilisahar about 3 years ago - 1 comment

#90 - Error in ExaNIC_X10 example design timing constrain file eth_mac_fifo.tcl

Issue - State: open - Opened by beyond2002 over 3 years ago - 1 comment

#89 - UDP complete waves

Issue - State: open - Opened by aignacio over 3 years ago - 10 comments

#88 - RGMII error on Spartan 6.

Issue - State: closed - Opened by apahm over 3 years ago - 1 comment

#88 - RGMII error on Spartan 6.

Issue - State: closed - Opened by apahm over 3 years ago - 1 comment

#87 - Receiving broken packets in U50

Issue - State: open - Opened by nunesedu over 3 years ago - 4 comments

#85 - Does LFSR module support 32-bit datawidth for 10G base-r screamble/descreamble?

Issue - State: open - Opened by beyond2002 over 3 years ago - 2 comments

#84 - Fix udp checksum header overflow

Pull Request - State: open - Opened by hannodewind over 3 years ago

#83 - [udp_checksum_gen_64]: header drop on header fifo overflow

Issue - State: open - Opened by hannodewind over 3 years ago - 1 comment

#83 - [udp_checksum_gen_64]: header drop on header fifo overflow

Issue - State: open - Opened by hannodewind over 3 years ago - 1 comment

#82 - no axis input while using rgmii_1g_fifo on Spartan-7

Issue - State: closed - Opened by Winters123 over 3 years ago - 4 comments

#81 - porting to VU440 with 88E1116

Issue - State: open - Opened by Albert-Siu over 3 years ago - 2 comments

#80 - Marvell Alaska 88e1512 support

Issue - State: open - Opened by AyeshaGauhar over 3 years ago - 3 comments

#79 - Question about flow control

Issue - State: closed - Opened by Yuan-Mao over 3 years ago - 5 comments
Labels: question

#78 - Add LAST_ENABLE parameter to axis-arb-mux

Pull Request - State: closed - Opened by jeehoonkang over 3 years ago - 2 comments

#78 - Add LAST_ENABLE parameter to axis-arb-mux

Pull Request - State: closed - Opened by jeehoonkang over 3 years ago - 2 comments

#77 - Added STLV7325 board

Pull Request - State: open - Opened by aignacio over 3 years ago - 3 comments

#76 - how to make it onto U50

Issue - State: open - Opened by fyflxl over 3 years ago - 3 comments

#76 - how to make it onto U50

Issue - State: open - Opened by fyflxl over 3 years ago - 3 comments

#75 - fix overflow in parameter sizes for ARP timeouts

Pull Request - State: open - Opened by AaronCleaver over 3 years ago - 2 comments

#75 - fix overflow in parameter sizes for ARP timeouts

Pull Request - State: open - Opened by AaronCleaver over 3 years ago - 2 comments

#74 - Tight timing in rgmii_phy_if.v

Issue - State: open - Opened by eugene-tarassov over 3 years ago - 3 comments

#74 - Tight timing in rgmii_phy_if.v

Issue - State: open - Opened by eugene-tarassov over 3 years ago - 3 comments

#73 - Cannot receive packets

Issue - State: open - Opened by abdullahyildiz over 3 years ago - 4 comments

#73 - Cannot receive packets

Issue - State: open - Opened by abdullahyildiz over 3 years ago - 4 comments

#72 - question about principle

Issue - State: open - Opened by AliceXuXu over 3 years ago - 7 comments

#71 - UDP Fragmentation

Issue - State: closed - Opened by Uroojt over 3 years ago - 8 comments

#70 - Netcat doing nothing

Issue - State: open - Opened by surelynottrue over 3 years ago - 13 comments

#70 - Netcat doing nothing

Issue - State: open - Opened by surelynottrue over 3 years ago - 13 comments

#69 - Where to get the x25 pin assignment document?

Issue - State: closed - Opened by JimmyJuan over 3 years ago - 3 comments

#69 - Where to get the x25 pin assignment document?

Issue - State: closed - Opened by JimmyJuan over 3 years ago - 3 comments

#68 - Query : runt Packets

Issue - State: open - Opened by kewlcreatures almost 4 years ago - 6 comments

#68 - Query : runt Packets

Issue - State: open - Opened by kewlcreatures almost 4 years ago - 6 comments

#67 - Strange issue with VCU118

Issue - State: open - Opened by np84 almost 4 years ago - 23 comments

#67 - Strange issue with VCU118

Issue - State: open - Opened by np84 almost 4 years ago - 23 comments

#66 - FCS errors on output port

Issue - State: open - Opened by asmir-abdulahovic almost 4 years ago - 2 comments

#65 - Broadcom® B50610 PHY chip support

Issue - State: open - Opened by pwang7 almost 4 years ago - 3 comments

#65 - Broadcom® B50610 PHY chip support

Issue - State: open - Opened by pwang7 almost 4 years ago - 3 comments

#64 - Xilinx Ultrascle+ GTY Reset issue

Issue - State: open - Opened by wfullmer12 almost 4 years ago - 4 comments

#64 - Xilinx Ultrascle+ GTY Reset issue

Issue - State: open - Opened by wfullmer12 almost 4 years ago - 4 comments

#63 - UDP Client

Issue - State: closed - Opened by dgarigali almost 4 years ago - 3 comments

#63 - UDP Client

Issue - State: closed - Opened by dgarigali almost 4 years ago - 3 comments

#62 - Add Xilinx VC709 example

Pull Request - State: open - Opened by wingel almost 4 years ago

#62 - Add Xilinx VC709 example

Pull Request - State: open - Opened by wingel almost 4 years ago

#61 - ip header checksum error?

Issue - State: closed - Opened by cws11 almost 4 years ago - 10 comments
Labels: question

#59 - How to make this project for C10LP

Issue - State: open - Opened by dennypig almost 4 years ago - 3 comments

#59 - How to make this project for C10LP

Issue - State: open - Opened by dennypig almost 4 years ago - 3 comments

#58 - lfsr module (eth_crc_8 instance) in the axis_gmii_rx module is not synthesizing correctly with Precision and Synplify Pro

Issue - State: open - Opened by tkunce almost 4 years ago - 5 comments
Labels: bug

#58 - lfsr module (eth_crc_8 instance) in the axis_gmii_rx module is not synthesizing correctly with Precision and Synplify Pro

Issue - State: open - Opened by tkunce almost 4 years ago - 5 comments
Labels: bug

#57 - eth_mac_1g_fifo rx bad bcs interrupt is not assigned correctly

Issue - State: closed - Opened by tkunce almost 4 years ago - 2 comments
Labels: bug

#56 - AXI config example

Issue - State: closed - Opened by mika94mes almost 4 years ago - 1 comment
Labels: question

#56 - AXI config example

Issue - State: closed - Opened by mika94mes almost 4 years ago - 1 comment
Labels: question

#55 - tx parameters

Issue - State: closed - Opened by nitya261 about 4 years ago - 4 comments
Labels: question

#54 - loopback

Issue - State: open - Opened by verilog123 about 4 years ago - 1 comment
Labels: question

#54 - loopback

Issue - State: open - Opened by verilog123 about 4 years ago - 1 comment
Labels: question

#53 - support 40G

Issue - State: open - Opened by beer-belly about 4 years ago - 6 comments
Labels: question

#52 - custom data

Issue - State: open - Opened by nitya261 about 4 years ago

#51 - Minor nits. Default state in mdio state case

Issue - State: open - Opened by secworks about 4 years ago

#50 - axis_eth_fcs modules example

Issue - State: closed - Opened by mika94mes about 4 years ago - 1 comment
Labels: question

#49 - subnet decision issue

Issue - State: open - Opened by Rhapso about 4 years ago - 2 comments
Labels: question

#48 - respond to ARP through direct connection but doesn't respond through the LAN Switch

Issue - State: closed - Opened by MichaelAstahov about 4 years ago - 5 comments

#47 - Unable to connect MII Ethernet interface with 1G/100M/10M switch

Issue - State: closed - Opened by MichaelAstahov about 4 years ago - 4 comments

#46 - eth_mac_mii_fifo module not fully working for me

Issue - State: closed - Opened by MichaelAstahov about 4 years ago - 4 comments

#45 - Making of Example Vivado Project

Issue - State: closed - Opened by FPGA-Bot-Yang about 4 years ago - 7 comments

GitHub / alexforencich/verilog-ethernet issues and pull requests