Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / alexforencich/verilog-axi issues and pull requests

#83 - it seem like axi_adapter not support outstanding transfer

Issue - State: open - Opened by DV-Carium about 2 months ago

#82 - axil_fifo

Issue - State: open - Opened by 0TulipRose0 3 months ago - 1 comment

#81 - `axi_dma_wr` does not respect TKEEP

Issue - State: open - Opened by KireinaHoro 3 months ago - 1 comment

#80 - axi_dma_wr seems to give done status before fully writing to DDR?

Issue - State: open - Opened by abarajithan11 4 months ago - 6 comments

#78 - Q: DMA, desc_len VS tlast in axi_dma_wr

Issue - State: open - Opened by abarajithan11 6 months ago - 3 comments

#77 - Performing multiple beat transfer

Issue - State: closed - Opened by ManjunathKalmath 6 months ago - 14 comments

#76 - about AXI DMA

Issue - State: open - Opened by zengzhengqi0524 6 months ago - 2 comments

#75 - cocotb makefile

Issue - State: closed - Opened by ManjunathKalmath 7 months ago - 2 comments

#74 - About AXI_FULL_CDC

Issue - State: open - Opened by LZR1567 8 months ago - 2 comments

#73 - about axi_ram

Issue - State: open - Opened by nViol3t 8 months ago - 2 comments

#72 - AXI_Register hangs when SIM=verilator

Issue - State: closed - Opened by ManjunathKalmath 8 months ago - 3 comments

#71 - Failed to run test for AXI RAM with DATA_WIDTH=64 and ADDR=64

Issue - State: closed - Opened by ManjunathKalmath 8 months ago - 4 comments

#70 - About the solution for deadlocks

Issue - State: open - Opened by omeag 9 months ago - 14 comments

#69 - about tb

Issue - State: open - Opened by Unicorn619 9 months ago - 1 comment

#68 - About width missmatch

Issue - State: open - Opened by a60626316 9 months ago - 2 comments

#67 - Timing issues with `axi_dma_wr`

Issue - State: open - Opened by KireinaHoro 10 months ago

#66 - Axi DMA consistently returns DECERR

Issue - State: open - Opened by EnricoGiordano1992 10 months ago - 6 comments

#65 - Will unprocessed awvalid signals be stored in AXI Crossbar?

Issue - State: open - Opened by omeag 10 months ago - 6 comments

#63 - about axi_ram design specification

Issue - State: open - Opened by Maani02 11 months ago

#62 - Add explicit python3 prefix to all python paths in test suite

Pull Request - State: open - Opened by dbarrie 11 months ago

#61 - Add explicit python3 prefix to all python paths in test suite

Pull Request - State: closed - Opened by dbarrie 11 months ago

#60 - Q: Do axi_dma_rd and axi_dma_wr support out of order transactions?

Issue - State: open - Opened by abarajithan11 about 1 year ago - 2 comments

#59 - about AXI_VFIFO

Issue - State: open - Opened by Monster-Kee about 1 year ago - 3 comments

#58 - I met a question about simulation, please some one help me?

Issue - State: closed - Opened by OldTomCrazyCode about 1 year ago - 2 comments

#57 - awready and wready set high in master without slave value

Issue - State: open - Opened by sazam0 over 1 year ago

#56 - Why assume packet smaller than max burst size when AXI_MAX_BURST_SIZE >=4096?

Issue - State: closed - Opened by qiweiii-git over 1 year ago - 10 comments

#55 - axi_interconnect Synthesis

Issue - State: open - Opened by GGbang2 over 1 year ago - 1 comment

#54 - AXI Lite interconnect in N to 1 configuration

Issue - State: open - Opened by Twistix over 1 year ago - 2 comments

#53 - AXI Reset Signal

Issue - State: open - Opened by mkokki over 1 year ago

#52 - About priority_encoder

Issue - State: open - Opened by GGbang2 over 1 year ago - 4 comments

#51 - AXI interconnect

Issue - State: open - Opened by ilamparithy01 over 1 year ago - 2 comments

#50 - Documentation for axil_interconnect

Issue - State: open - Opened by catkira over 1 year ago - 3 comments

#49 - Fix AXI_ADDR_BIT_OFFSET and AXIL_ADDR_BIT_OFFSET part select

Pull Request - State: open - Opened by AlexLao512 over 1 year ago - 6 comments

#48 - AxiLiteMaster hangs with Verilator

Issue - State: open - Opened by catkira over 1 year ago - 14 comments

#47 - WIP: Verilator Compatibility

Pull Request - State: open - Opened by benreynwar over 1 year ago

#46 - axil_adapter_wr : Modelsim error "part select is reversed"

Issue - State: open - Opened by peioazk over 1 year ago - 8 comments

#45 - tb simulation failed

Issue - State: open - Opened by nashsrg over 1 year ago - 2 comments

#44 - AXIL crossbar doesn't support M_ADDR_WIDTH < 12

Issue - State: open - Opened by martin-tanguay over 1 year ago - 8 comments

#43 - Does the AXI bus adapter support the downsizer from 256bits to 8bits？

Issue - State: closed - Opened by chengquan almost 2 years ago - 12 comments

#42 - add option for initialization file for RAM

Pull Request - State: open - Opened by bunnie almost 2 years ago

#41 - fix numerical overflow in bit shift operation

Pull Request - State: open - Opened by bunnie almost 2 years ago

#40 - Disable verilator lint warnings

Pull Request - State: closed - Opened by zhizhenzhong almost 2 years ago

#39 - fix vivado synthesis problems in axil_reg_if_wr.v

Pull Request - State: closed - Opened by jameyhicks about 2 years ago - 7 comments

#38 - Parametrization doesn't work correctly in testbenches

Issue - State: closed - Opened by vkomenda about 2 years ago - 2 comments

#37 - axi_adapter: fix compilation with verilator

Pull Request - State: closed - Opened by sergachev over 2 years ago - 7 comments

#36 - axil_ram. How to adjust rvaild delay.

Issue - State: closed - Opened by cjhonlyone over 2 years ago

#35 - question: how to read this syntax?

Issue - State: closed - Opened by hughperkins over 2 years ago - 2 comments

#34 - Circular logic in axi_crossbar

Issue - State: open - Opened by MikeWalrus over 2 years ago

#33 - AXI DMA never gives out a ready HIGH

Issue - State: open - Opened by jasonzzzzzzz over 2 years ago - 1 comment

#32 - About CDMA testbench with AXI_DATA_WIDTH > 64

Issue - State: closed - Opened by swleungbrian over 2 years ago - 2 comments

#31 - AXI interconnect/crossbar hanging while mult. writes

Issue - State: open - Opened by aignacio over 2 years ago - 4 comments

#30 - Support read data interleaving

Issue - State: open - Opened by alexforencich almost 3 years ago

#29 - Question on address decoder to determine master interface

Issue - State: closed - Opened by Pi-Turn almost 3 years ago - 6 comments

#28 - Range of part-select into 'addr_reg' is reversed, modelsim error in axi_adapter

Issue - State: open - Opened by Takasa about 3 years ago - 4 comments

#27 - Fix readme typo

Pull Request - State: open - Opened by FlyGoat about 3 years ago

#26 - About axil-interconnect

Issue - State: open - Opened by omeag about 3 years ago - 6 comments

#25 - CDC module

Issue - State: open - Opened by omeag about 3 years ago - 2 comments

#24 - About VCS Compile

Issue - State: open - Opened by dybzcx about 3 years ago - 1 comment

#23 - About CDC module

Issue - State: open - Opened by omeag about 3 years ago - 3 comments

#22 - application problem

Issue - State: open - Opened by tuuyii about 3 years ago - 2 comments

#21 - questions about axicrossbar

Issue - State: open - Opened by omeag over 3 years ago - 21 comments

#20 - questions about data transfer order

Issue - State: open - Opened by Hang-XX over 3 years ago - 5 comments

#19 - Correct understanding of axi_dma

Issue - State: closed - Opened by aignacio over 3 years ago - 2 comments

#18 - How to get waves from the tbs

Issue - State: closed - Opened by aignacio over 3 years ago - 4 comments

#17 - BRAM inference for Xilinx FPGAs

Issue - State: closed - Opened by aignacio over 3 years ago - 11 comments

#16 - axi_interconnect question

Issue - State: closed - Opened by aignacio over 3 years ago - 8 comments

#15 - where is s_axi_wlast ?

Issue - State: open - Opened by Ellen7ions over 3 years ago - 2 comments

#14 - axil_ram handshake between AW/AR-READY and B/R-RESP

Issue - State: open - Opened by jimmysitu over 3 years ago - 3 comments

#13 - Long logic depth leads to bad timing

Issue - State: open - Opened by luyong6 almost 4 years ago - 6 comments

#12 - Bug in 4K boundary crossing detection in DMA modules

Issue - State: closed - Opened by luyong6 about 4 years ago - 8 comments
Labels: bug

#11 - Updated AXI-lite RAM to pass a formal verification check

Pull Request - State: open - Opened by ZipCPU about 4 years ago - 1 comment

#10 - Missing WID signal in axi_ram

Issue - State: closed - Opened by chenguokai about 4 years ago

#9 - questions about about the AXI_DMA module

Issue - State: open - Opened by Taohua-digital over 4 years ago - 10 comments

#8 - axi_ram module triggers violation in Xilinx AXI Protocol Checker

Issue - State: open - Opened by buttercutter over 4 years ago - 11 comments

#7 - Endianness of axis_fifo_adapter

Issue - State: closed - Opened by pfrankis over 4 years ago

#6 - Fix counter reset

Pull Request - State: closed - Opened by kermit0124 almost 5 years ago - 3 comments

#5 - question about axi_ram

Issue - State: closed - Opened by yhw1993 almost 5 years ago - 1 comment
Labels: duplicate

#4 - question about axi_ram

Issue - State: closed - Opened by yhw1993 almost 5 years ago - 1 comment
Labels: bug

#3 - Query: Maximum number of outstanding read request

Issue - State: open - Opened by msharmavikram almost 5 years ago - 1 comment
Labels: question

#2 - Verilog axi synthesizable protocol checker

Issue - State: open - Opened by chips4yu about 5 years ago - 1 comment
Labels: question

#1 - Quick question about clock domain crossing (CDC)

Issue - State: closed - Opened by olagrottvik over 5 years ago - 10 comments
Labels: enhancement