VLSIDA/OpenRAM issues and pull requests

#145 - Add nand4_leakage to sky130

Pull Request - State: open - Opened by ja5087 about 2 years ago

#144 - SRAM Simulation Codes

Issue - State: closed - Opened by BYCakar about 2 years ago - 6 comments

#143 - OpenRAM Macros DRC Violations in OpenLane

Issue - State: closed - Opened by mousaq92 about 2 years ago - 1 comment

#142 - Calculation of latency, throughput and memory access time

Issue - State: closed - Opened by tirumalnaidu about 2 years ago - 1 comment

#141 - LVS Errors with Sky130 SRAMs

Issue - State: closed - Opened by BYCakar about 2 years ago - 3 comments

#140 - SRAM macros for Open MPW

Issue - State: closed - Opened by BYCakar about 2 years ago - 6 comments

#139 - Execution performance of OpenRAM

Issue - State: closed - Opened by FJShen about 2 years ago - 6 comments

#138 - Must define either `fet_libaries` or `fet_models` error

Issue - State: closed - Opened by IanBoyanZhang about 2 years ago - 1 comment

#137 - Total cols must be divisible by 2

Issue - State: closed - Opened by IanBoyanZhang about 2 years ago - 2 comments

#136 - Remove SRAM_LIBRARY folder when cleanning up

Pull Request - State: open - Opened by IanBoyanZhang about 2 years ago

#135 - Read Data Out Characteristics

Issue - State: closed - Opened by stephenry about 2 years ago - 3 comments

#134 - Clock frequency

Issue - State: closed - Opened by cansudemirkiran over 2 years ago - 3 comments

#133 - SRAM Macros for MPW Designs

Issue - State: open - Opened by mousaq92 over 2 years ago - 1 comment

#132 - Can this complier generate arrays with customized SRAM cells?

Issue - State: closed - Opened by AlwaysWry over 2 years ago - 5 comments

#131 - README: Fix example in Basic Usage

Pull Request - State: closed - Opened by dnltz over 2 years ago

#130 - feature: support for unaligned access with special address increment pin

Issue - State: closed - Opened by jeras over 2 years ago - 7 comments

#129 - "LVS mismatch" occurs when running example_configs

Issue - State: open - Opened by jingyao-zhang over 2 years ago - 4 comments

#128 - How can I generate dual port SRAM

Issue - State: closed - Opened by microSharjeel over 2 years ago - 9 comments

#127 - sram attribute has no attribute 'control size'

Issue - State: closed - Opened by MaestroLiu3 over 2 years ago - 3 comments

#126 - Delay in generated SRAM

Issue - State: closed - Opened by Jianfengusa over 2 years ago - 3 comments

#125 - v1.1.19 finishes without outputs

Issue - State: closed - Opened by evmanz over 2 years ago - 5 comments

#124 - Verilog files issue

Issue - State: closed - Opened by nayiri-k over 2 years ago - 1 comment

#123 - Can't find Sky130 bitcell

Issue - State: closed - Opened by bkoppelmann almost 3 years ago - 3 comments

#122 - Use another PDK

Issue - State: closed - Opened by robert00091 almost 3 years ago - 1 comment

#121 - Fix Verilog

Pull Request - State: closed - Opened by erendn almost 3 years ago

#120 - Memory access energy

Issue - State: closed - Opened by rubenheyrman almost 3 years ago - 2 comments

#119 - Error in converting .lib to .db with lc_shell

Issue - State: open - Opened by imhjnju about 3 years ago

#118 - Frequency for power numbers in report

Issue - State: closed - Opened by oscargus about 3 years ago - 3 comments

#117 - Verilog model features

Pull Request - State: closed - Opened by olofk about 3 years ago - 1 comment

#116 - Fixes to support TSMC18 technology port

Pull Request - State: open - Opened by ckdur about 3 years ago - 1 comment

#115 - regression test fail: subunit file missing

Issue - State: closed - Opened by bvhoof over 3 years ago - 6 comments

#114 - Write enable rbl_bl_delay_bar to rbl_bl_delay

Pull Request - State: closed - Opened by lekez2005 over 3 years ago - 5 comments

#113 - Potential bug in control logic write enable

Issue - State: closed - Opened by lekez2005 over 3 years ago - 4 comments

#112 - Generating memory with 1R 1W port throws an error on Master branch

Issue - State: closed - Opened by aparna1996 over 3 years ago - 2 comments

#111 - freepdk using calibre lvs: top level ports issue

Issue - State: closed - Opened by bvhoof over 3 years ago - 3 comments

#110 - Dev: fix issues to run using freepdk45

Pull Request - State: closed - Opened by bvhoof over 3 years ago

#108 - Error occurred while determining bitline names. Can cause faults in simulation.

Issue - State: closed - Opened by mguthaus over 3 years ago - 2 comments

#107 - Operating conditions in corners are wrong

Issue - State: closed - Opened by mguthaus over 3 years ago - 5 comments

#103 - Check the right netgen is installed

Issue - State: closed - Opened by mithro over 3 years ago - 1 comment

#102 - Minor typo in README.md

Pull Request - State: closed - Opened by dpetrisko over 3 years ago - 1 comment

#98 - [Enhancement] A less dense power grid is needed to automate power routing

Issue - State: closed - Opened by ax3ghazy over 3 years ago - 1 comment

#93 - Fix missing import in hierarchy_layout file.

Pull Request - State: closed - Opened by mithro over 3 years ago - 1 comment

#91 - Remove all line ending white space (and check to prevent it coming back)

Issue - State: closed - Opened by mithro over 3 years ago
Labels: help wanted

#85 - fix regession tests after calibre fix

Pull Request - State: closed - Opened by bvhoof almost 4 years ago - 1 comment

#67 - Error while generating 16 x 16 Array

Issue - State: closed - Opened by GyanendraTiwari over 4 years ago - 4 comments

#54 - Add list of papers which use / reference OpenRAM

Issue - State: closed - Opened by mithro over 4 years ago - 2 comments

#49 - Could Xyce be used in OpenRAM?

Issue - State: closed - Opened by mithro almost 5 years ago - 2 comments

#48 - Multi-bank support

Issue - State: closed - Opened by robin-tukl almost 5 years ago - 8 comments

#41 - Feature: dual port SAM (sequential access memory)

Issue - State: closed - Opened by jeras almost 6 years ago - 3 comments
Labels: enhancement

GitHub / VLSIDA/OpenRAM issues and pull requests