Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / UCSBarchlab/PyRTL issues and pull requests

#438 - Bump jinja2 from 3.1.2 to 3.1.3 in /docs

Pull Request - State: closed - Opened by dependabot[bot] 11 months ago
Labels: dependencies

#437 - Bump urllib3 from 2.0.6 to 2.0.7 in /docs

Pull Request - State: closed - Opened by dependabot[bot] about 1 year ago - 1 comment
Labels: dependencies

#436 - Experiment with Furo theme for PyRTL's documentation.

Pull Request - State: closed - Opened by fdxmw about 1 year ago - 1 comment

#434 - Bump urllib3 from 2.0.4 to 2.0.6 in /docs

Pull Request - State: closed - Opened by dependabot[bot] about 1 year ago - 2 comments
Labels: dependencies

#433 - WireVector name setter unit test added

Pull Request - State: closed - Opened by TonyKorol1 about 1 year ago - 1 comment

#431 - Bump certifi from 2023.5.7 to 2023.7.22 in /docs

Pull Request - State: closed - Opened by dependabot[bot] over 1 year ago - 1 comment
Labels: dependencies

#430 - Bump requests from 2.30.0 to 2.31.0 in /docs

Pull Request - State: closed - Opened by dependabot[bot] over 1 year ago
Labels: dependencies

#429 - Migrate from nose to pytest and enable testing on Python 3.11.

Pull Request - State: closed - Opened by fdxmw over 1 year ago - 2 comments

#428 - Assorted WaveRenderer UI improvements

Pull Request - State: closed - Opened by fdxmw about 2 years ago - 6 comments

#427 - Added Module name change functionality for Issue #420

Pull Request - State: open - Opened by spencercheese about 2 years ago

#426 - Fix tox tests on arm64:

Pull Request - State: closed - Opened by fdxmw about 2 years ago - 1 comment

#425 - A collection of changes that should make tox runs pass

Pull Request - State: closed - Opened by fdxmw about 2 years ago

#424 - render_trace()'s default symbol_len should be None rather than 5 to e…

Pull Request - State: closed - Opened by fdxmw about 2 years ago - 1 comment

#423 - ROM not working as expected (16 bit address & 16 bit data)

Issue - State: closed - Opened by kfeiste about 2 years ago - 1 comment

#422 - Wires used but never driven

Issue - State: open - Opened by JulianKemmerer over 2 years ago - 6 comments

#421 - Python 3.10 Support

Issue - State: open - Opened by benjaminmordaunt over 2 years ago - 1 comment
Labels: working in development branch

#420 - "toplevel" in verilog output is hardcoded

Issue - State: open - Opened by bjourne over 2 years ago
Labels: enhancement, beginner friendly

#419 - Fix typo in WireVector getitem

Pull Request - State: closed - Opened by ezhang7423 over 2 years ago - 1 comment

#418 - Add bitmasked write to memories

Issue - State: open - Opened by timsherwood over 2 years ago - 1 comment

#417 - fixed point

Issue - State: open - Opened by timsherwood over 2 years ago - 1 comment
Labels: enhancement

#416 - Support newer Python graphviz module

Pull Request - State: closed - Opened by ryoon over 2 years ago - 2 comments

#415 - Add documentation for Block class public methods

Pull Request - State: closed - Opened by strongwar over 2 years ago - 3 comments

#414 - Add unit tests for different types of possible flip-flops importable as BLIF

Issue - State: open - Opened by mdko almost 3 years ago - 1 comment

#413 - Improve BLIF importer to handle more types of dffs

Pull Request - State: closed - Opened by mdko almost 3 years ago - 2 comments

#412 - Import ABC from collections.abc for Python 3.10 compatibility.

Pull Request - State: closed - Opened by tirkarthi almost 3 years ago - 1 comment

#411 - Missing SDFF_PP1 circuit model yosys primitive

Issue - State: closed - Opened by JulianKemmerer almost 3 years ago - 5 comments

#410 - Import `collections.abc.Mapping`

Issue - State: closed - Opened by corwin-of-amber almost 3 years ago - 2 comments

#409 - Remove Python 2 support

Pull Request - State: open - Opened by mdko almost 3 years ago

#408 - Fix minor typo in `Registers` documentation

Pull Request - State: closed - Opened by SwiftWinds almost 3 years ago - 1 comment

#407 - Fix constant propagation for unsynthesized blocks

Pull Request - State: closed - Opened by mdko about 3 years ago

#406 - Find better way to handle special WireVector subclasses like `_MemIndexed`

Issue - State: open - Opened by mdko about 3 years ago
Labels: confusing or uncaught error

#405 - Return special dictionaries from `net_connections()`.

Pull Request - State: closed - Opened by mdko about 3 years ago

#404 - Implement a language agnostic hardware representation

Pull Request - State: open - Opened by RhysGretsch81 about 3 years ago - 4 comments

#403 - Improve paths() function, more tests, small update on trailing whitespace when printing a net

Pull Request - State: closed - Opened by mdko about 3 years ago - 1 comment

#402 - Make paths() function match docs

Pull Request - State: closed - Opened by mdko about 3 years ago - 1 comment

#401 - Don't generate nands on BLIF import

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#400 - Improve Verilog output when a memory doesn't have any writes

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#399 - Improve rom verilog output

Pull Request - State: closed - Opened by vegaluisjose over 3 years ago - 3 comments

#397 - Improve binary wave form in Ascii trace render

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#396 - Use `-V` for checking yosys, rather than `--version`, for more compatibility

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#395 - Add ability to specify dont-cares in expected output of step_multiple

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#394 - Fix html trace visualization when value is a boolean and/or supplied …

Pull Request - State: closed - Opened by mdko over 3 years ago - 2 comments

#393 - Convenience function for importing Verilog into PyRTL via the Yosys/BLIF workflow

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#391 - Small adjustment for code clarity

Pull Request - State: closed - Opened by mdko over 3 years ago

#390 - Add ability to specify how values render in trace; improve symbol_len calculation.

Pull Request - State: closed - Opened by mdko over 3 years ago - 3 comments

#389 - Feed sanity check flag during optimization to subpasses

Pull Request - State: closed - Opened by mdko over 3 years ago

#388 - Simplify BLIF cover import to be more programmatic

Pull Request - State: closed - Opened by mdko over 3 years ago

#387 - More tests, documentation for bitfield_update (incl. set)

Pull Request - State: closed - Opened by mdko over 3 years ago

#386 - Add add_reset to verilog test bench generation, and add check for existing `rst` wire.

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#385 - Fix bug when add_reset=False; add Register tests

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#384 - Adding automatic reset for registers

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#383 - Enable code coverage

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#382 - Add sanity checks for wirevector_by_name

Pull Request - State: closed - Opened by mdko over 3 years ago

#381 - Update website example graph images

Pull Request - State: closed - Opened by mdko over 3 years ago

#380 - Update AES example

Pull Request - State: closed - Opened by mdko over 3 years ago

#379 - AES example not executable

Issue - State: closed - Opened by jemcmahan13 over 3 years ago

#378 - Add graphviz as Binder (Jupyter) dependency

Pull Request - State: closed - Opened by mdko over 3 years ago

#377 - fixed references to estimate.py code

Pull Request - State: closed - Opened by normanpatrick over 3 years ago - 1 comment

#376 - Add automatic testing of Jupyter notebook files

Issue - State: open - Opened by mdko over 3 years ago - 1 comment
Labels: testing

#375 - Documentation missing interface for Block

Issue - State: open - Opened by timsherwood over 3 years ago
Labels: beginner friendly

#374 - Add optimization pass that removes unneeded slices

Pull Request - State: closed - Opened by mdko over 3 years ago

#373 - Rename ISCAS bench output wires if also an input

Pull Request - State: closed - Opened by mdko over 3 years ago

#372 - Add ISCAS benchmark importer

Pull Request - State: closed - Opened by mdko over 3 years ago

#371 - Move and improve list_to_int helper from test_matrix.py to matrix.py file

Pull Request - State: closed - Opened by mdko over 3 years ago

#370 - Register update on Negative edge

Issue - State: closed - Opened by tahaghauri over 3 years ago - 1 comment

#369 - Fix Matrix, flatten(), add reshape() and put() methods

Pull Request - State: closed - Opened by mdko over 3 years ago

#368 - Minor fix to distance() analysis function

Pull Request - State: closed - Opened by mdko over 3 years ago

#366 - Add flatten() method to matrices

Pull Request - State: closed - Opened by mdko over 3 years ago

#364 - Make graphviz string export deterministic via ordering the nodes first

Pull Request - State: closed - Opened by mdko over 3 years ago

#362 - Minor fix to replace_wires_fast

Pull Request - State: closed - Opened by mdko over 3 years ago

#361 - Add optional pass for making all fanouts <= 2

Pull Request - State: closed - Opened by mdko over 3 years ago

#360 - Add optional pass directly connecting nets to outputs when possible

Pull Request - State: closed - Opened by mdko over 3 years ago

#359 - fix comment

Pull Request - State: closed - Opened by mdko over 3 years ago

#358 - Be able to show multiplicity of identical edges going to a net

Pull Request - State: closed - Opened by mdko over 3 years ago - 2 comments

#357 - Graph output doesn't display multiple identical edges properly

Issue - State: closed - Opened by mdko over 3 years ago

#356 - Allow integer shift amounts for shifter corecircuits

Pull Request - State: closed - Opened by mdko over 3 years ago

#355 - Implement wrap_around in the barrel_shifter

Issue - State: open - Opened by mdko over 3 years ago
Labels: fix before version 1.0

#353 - Determinize verilog testbench output

Pull Request - State: closed - Opened by mdko over 3 years ago

#352 - Some basic graph-related algorithms

Pull Request - State: closed - Opened by mdko over 3 years ago

#351 - Cleanup directories, consolidate and rename files.

Pull Request - State: closed - Opened by mdko over 3 years ago

#350 - A different way of specifying conditional defaults

Pull Request - State: closed - Opened by mdko over 3 years ago

#349 - Updating `clone_wire` to be safe when used on same block.

Pull Request - State: closed - Opened by mdko over 3 years ago

#347 - Remove `replace_wire`, use `replace_wire_fast` instead; add tests and more documentation

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#346 - Adding documentation and some tests for the passes and transforms

Pull Request - State: closed - Opened by mdko over 3 years ago

#344 - Put all io-related code into new inputoutput directory, splitting up original file as needed

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#343 - Improve how bit selects and memory ops are presented in graphviz

Pull Request - State: closed - Opened by mdko over 3 years ago - 1 comment

#291 - added matrices to PyRTL

Pull Request - State: closed - Opened by dkupsh about 4 years ago - 6 comments

#273 - Wavedrom output issues

Issue - State: closed - Opened by ti6wb over 4 years ago - 1 comment