SystemRDL/PeakRDL-regblock issues and pull requests

#123 - [QUESTION] Self-clearing regblock reset

Issue - State: open - Opened by philipaxer 21 days ago

#122 - [FEATURE]Reduce the CPU_IF logic, use only AXI LITE

Issue - State: open - Opened by roybod about 1 month ago

#121 - VHDL Field Logic

Pull Request - State: closed - Opened by darsor about 1 month ago - 1 comment

#120 - [BUG] intr field can miss events during SW writes

Issue - State: open - Opened by hughjackson about 2 months ago - 1 comment

#119 - [FEATURE] AHB interface support

Issue - State: open - Opened by Blebowski about 2 months ago - 3 comments
Labels: feature request

#118 - [BUG] software read-only, hardware write-only not working with write enable

Issue - State: open - Opened by miguel9554 3 months ago

#117 - Fix spyglass warning and add options

Pull Request - State: open - Opened by mmk-sc 4 months ago

#116 - [BUG] Incorred bit extraction on external component address assignment

Issue - State: open - Opened by apstrike 4 months ago

#115 - [BUG] reg after external mem is only generated if not in regfile or addrmap

Issue - State: open - Opened by paul-demo 5 months ago

#114 - Saturating counters perform inequality check twice in generated logic

Issue - State: open - Opened by paul-demo 6 months ago

#113 - [BUG] Genus unsynthesizable error on rising/falling edge interrupt field

Issue - State: open - Opened by BertVerrycken 6 months ago

#112 - [FEATURE] Parameters in regblock package

Issue - State: open - Opened by benoitdenkinger 6 months ago

#111 - External registers packed struct

Issue - State: open - Opened by benoitdenkinger 6 months ago - 1 comment

#110 - [BUG] memory size is not calulated correctly

Issue - State: open - Opened by arnonsha 6 months ago - 4 comments
Labels: invalid

#109 - [FEATURE] External register fields

Issue - State: closed - Opened by benoitdenkinger 6 months ago - 1 comment

#108 - src: Deduplicate read enable generation.

Pull Request - State: closed - Opened by Blebowski 7 months ago - 4 comments

#107 - Сpuif error response, when the address is decoded incorrectly

Pull Request - State: open - Opened by 3FoH9l 7 months ago

#106 - Fine-grained access rights

Issue - State: closed - Opened by Blebowski 7 months ago - 2 comments
Labels: question

#105 - Parity on R/W registers

Issue - State: closed - Opened by Blebowski 7 months ago - 2 comments
Labels: duplicate

#104 - Put pragmas around assertions

Issue - State: open - Opened by Blebowski 7 months ago - 2 comments

#103 - More optimized readback stage RTL generation

Issue - State: open - Opened by Blebowski 7 months ago - 4 comments
Labels: invalid, wontfix

#102 - Clock gating support

Issue - State: open - Opened by Blebowski 7 months ago - 4 comments
Labels: wontfix

#101 - Unaligned external addressable components

Issue - State: open - Opened by maltaisn 7 months ago

#100 - Interface data width vs register width vs access width

Issue - State: open - Opened by jscheid-ventana 7 months ago - 1 comment

#99 - hwset on multibit field

Issue - State: open - Opened by darrylring 7 months ago - 5 comments
Labels: feature request

#98 - Allow for WE/WEL in sticky/stickybit fields

Pull Request - State: open - Opened by mtdudek 8 months ago - 3 comments

#97 - External mem state machine gets confused by rd_ack that may result from READ_FIRST BRAMs

Issue - State: closed - Opened by paul-demo 8 months ago - 3 comments

#96 - Timing of swmod seems 1 cycle too early

Issue - State: closed - Opened by paul-demo 8 months ago - 2 comments
Labels: invalid

#95 - Files generated by this project do not work with Verilator

Issue - State: closed - Opened by paul-demo 8 months ago - 3 comments

#94 - SW = rw, HW = rw behavior seems incorrect

Issue - State: closed - Opened by paul-demo 8 months ago - 3 comments
Labels: question

#93 - unconditional is None # Can only have one unconditional assignment per field

Issue - State: open - Opened by xachb 8 months ago - 2 comments
Labels: bug

#92 - Casting For-Loop Iterator to Match Address Width in Decoding Logic

Issue - State: open - Opened by leolitenstorrent 8 months ago

#91 - Request to change from typdef enum int to typedef enum logic to resolve Lint Issues.

Issue - State: closed - Opened by amullick007 8 months ago - 5 comments
Labels: feature request

#90 - infer accesswidth when only external components in RDL

Issue - State: open - Opened by saberxt 8 months ago - 4 comments

#89 - make field_logic.get_next_q_identifier register independent of reset

Pull Request - State: open - Opened by aszakacs 8 months ago - 2 comments

#88 - Fix `regwidth` & `accesswidth` on buffer triggers when trigger is a `RegNode`

Pull Request - State: closed - Opened by apstrike 8 months ago - 1 comment

#87 - Spyglass issues with PeakRDL's CSR generated RTL

Issue - State: closed - Opened by NajamKhalil 9 months ago - 10 comments
Labels: feature request, invalid

#86 - fix: a typo in SV template

Pull Request - State: closed - Opened by motchy869 9 months ago

#85 - Support for iverilog

Issue - State: closed - Opened by shareefj 10 months ago - 4 comments
Labels: wontfix

#84 - External register fields in structs

Issue - State: closed - Opened by mpriestleyidex 10 months ago - 3 comments
Labels: feature request

#83 - Issue: Error in RegblockExporter.export regarding buffer_writes

Issue - State: closed - Opened by xcfuisnewhere 10 months ago - 4 comments
Labels: invalid

#82 - Bus AMBA APB3 and APB4 have PENABLE signal, but there isn't usage of it in RTL generation file (regblock)

Issue - State: closed - Opened by AaronPham0701 11 months ago - 7 comments
Labels: invalid

#81 - Cpuif properties

Pull Request - State: open - Opened by RasmusGOlsen 11 months ago

#80 - Add support for CPUIFs to have parameters

Pull Request - State: closed - Opened by hughjackson 11 months ago - 2 comments

#79 - missing we property in struct register defenition

Issue - State: closed - Opened by nirb82 11 months ago

#78 - Change SV sturcts to packed

Pull Request - State: closed - Opened by UniDanny 11 months ago

#77 - User defined property for specifying cpuif

Issue - State: open - Opened by RasmusGOlsen 12 months ago - 1 comment

#76 - Raising an error for unauthorized read or write

Issue - State: open - Opened by imerkado91 12 months ago - 6 comments
Labels: feature request

#75 - Intel Quartus support

Issue - State: closed - Opened by eruanno123 about 1 year ago - 1 comment
Labels: question

#74 - bug: Incorrect RTL for async reset when field does not have a reset value.

Issue - State: closed - Opened by jahagirdar about 1 year ago

#73 - During export, check for identifier collisions in output

Issue - State: open - Opened by amykyta3 about 1 year ago
Labels: feature request

#72 - Atomic accesses to memory components

Issue - State: closed - Opened by apstrike about 1 year ago - 2 comments

#71 - Default Value of a Read-Only Field is Generated as a Constant

Issue - State: closed - Opened by kdstrike about 1 year ago - 1 comment
Labels: bug

#70 - Fix incorrect struct type name generation when component is parameterized

Issue - State: closed - Opened by amykyta3 about 1 year ago - 1 comment
Labels: bug

#69 - using write/read suffixes instead of input/output for HW interface

Issue - State: closed - Opened by jeras about 1 year ago - 3 comments
Labels: wontfix

#68 - Fixing write strobe width

Pull Request - State: closed - Opened by mghibaudi about 1 year ago - 3 comments

#67 - Replacing `wire` (only used for input ports) with `logic`

Pull Request - State: closed - Opened by jeras about 1 year ago - 1 comment

#66 - Thoughts on address decoder implementation

Issue - State: closed - Opened by jeras about 1 year ago - 1 comment

#65 - Proposal to use `logic` instead of `wire` for module inputs

Issue - State: closed - Opened by jeras about 1 year ago - 4 comments
Labels: invalid

#64 - Support for packed structs

Issue - State: closed - Opened by leolitenstorrent about 1 year ago - 2 comments

#63 - Vivado Synthesis Compatability

Issue - State: closed - Opened by roowatt about 1 year ago - 3 comments
Labels: bug

#62 - packed structs instead of unpacked structs

Issue - State: closed - Opened by dale40 about 1 year ago - 1 comment
Labels: wontfix

#61 - VHDL Package Compatibilty

Issue - State: open - Opened by eddlestar over 1 year ago - 2 comments
Labels: feature request

#60 - Lower bits of cpu addr bus not ignored with wider data bus

Issue - State: closed - Opened by roowatt over 1 year ago - 4 comments
Labels: bug

#59 - Address is scaled for long register (regwidth > accesswidth)

Issue - State: closed - Opened by always-debug over 1 year ago - 5 comments
Labels: question

#58 - Omit unecessary hwif signals if an external register is read-only or write-only

Issue - State: closed - Opened by amykyta3 over 1 year ago - 3 comments
Labels: feature request

#57 - External Regfile not honoring wr_ack

Issue - State: closed - Opened by roowatt over 1 year ago - 6 comments
Labels: invalid

#56 - RCLR of a field at the same cycle as WE next value

Issue - State: closed - Opened by Risto97 over 1 year ago - 1 comment

#55 - Use literals of the same size in comparisons

Issue - State: closed - Opened by leolitenstorrent over 1 year ago - 3 comments
Labels: wontfix

#54 - Use scalar if conditions

Issue - State: closed - Opened by leolitenstorrent over 1 year ago - 3 comments
Labels: bug

#53 - Divide by zero for nested addrmaps

Issue - State: closed - Opened by ion-concepts over 1 year ago - 4 comments
Labels: bug

#52 - Instantiation stub to use generated RTL

Issue - State: closed - Opened by arhum-alam over 1 year ago - 2 comments
Labels: question

#51 - PeakRDL-regblock AXI-Lite prematurely asserting wready/awready when it can't handle new wdata/awdata

Issue - State: closed - Opened by arhum-alam over 1 year ago - 1 comment
Labels: invalid

#50 - Removing "if(1)" Conditions

Issue - State: closed - Opened by leolitenstorrent over 1 year ago - 2 comments
Labels: feature request

#49 - Making bit widths of vectors the same when doing comparisons

Issue - State: closed - Opened by leolitenstorrent over 1 year ago - 3 comments
Labels: feature request

#48 - How to create CSR's software access property controlled by hardware ?

Issue - State: closed - Opened by DerekWangScaleflux over 1 year ago - 2 comments
Labels: question

#47 - Feature Request: Option to remove buffer stage from AXI read/write

Issue - State: open - Opened by leolitenstorrent over 1 year ago - 6 comments
Labels: feature request

#46 - Address line width off-by-one

Issue - State: closed - Opened by leolitenstorrent over 1 year ago - 1 comment
Labels: bug

#45 - fatal: Incompatible assignment to property 'hwenable'

Issue - State: closed - Opened by rakesh2215 over 1 year ago - 1 comment
Labels: invalid

#44 - Is external memory/register supported ?

Issue - State: closed - Opened by DerekWangScaleflux over 1 year ago - 5 comments
Labels: invalid

#43 - Integer literals should be sized to avoid 32-bit truncation

Issue - State: closed - Opened by mkahane over 1 year ago - 2 comments
Labels: bug

#42 - swmod early?

Issue - State: closed - Opened by xachb over 1 year ago - 3 comments
Labels: question

#41 - Verilator support

Issue - State: open - Opened by Risto97 over 1 year ago - 6 comments

#40 - Add support for Avalon memory mapped peripherals

Issue - State: closed - Opened by Jan-Snoeijs over 1 year ago - 8 comments
Labels: feature request

#39 - Buffered write, trigger is a field of the register

Issue - State: closed - Opened by Risto97 over 1 year ago - 3 comments
Labels: feature request

#38 - Store previous data and the strobe in wbuf_storage

Pull Request - State: closed - Opened by Risto97 over 1 year ago - 2 comments

#37 - Add support for write broadcasting

Issue - State: open - Opened by amykyta3 over 1 year ago
Labels: feature request

#36 - External memory connections

Issue - State: closed - Opened by davidp135 over 1 year ago - 15 comments
Labels: duplicate

#35 - Parity Implementation (with preferably per-register storage, not per-field)

Issue - State: closed - Opened by galaviel over 1 year ago - 13 comments
Labels: feature request

#34 - Add override for all resets to be asynchronous by default

Issue - State: closed - Opened by galaviel over 1 year ago - 8 comments
Labels: feature request

#33 - Emit Parametrized PeakRDL output

Issue - State: open - Opened by galaviel over 1 year ago - 24 comments
Labels: feature request

#32 - Add support for alias registers

Issue - State: open - Opened by amykyta3 over 1 year ago - 1 comment
Labels: feature request

#31 - Enum support

Pull Request - State: closed - Opened by hughjackson over 1 year ago - 1 comment

#30 - peakrdl_regblock\exporter.py does not create output directory before trying to write .sv files

Issue - State: closed - Opened by craigc40 over 1 year ago - 2 comments

#29 - Add support for field encoding property

Issue - State: closed - Opened by apstrike over 1 year ago - 6 comments
Labels: feature request

#28 - the hw write not have control signal，it always true ，the code ： end else if(1) begin // HW Write next_c = hwif_in.test_excel1.cfg_reg.port2_role.next; load_next_c = '1;

Issue - State: closed - Opened by jiangqingliu88 almost 2 years ago - 2 comments
Labels: question

#27 - when i use peakrdl to test this generic_example .rdl,it will has"external chip_id chip_id_reg @0x0000;"error,do peakrdl dose not support the keyword of “external”？

Issue - State: closed - Opened by jiangqingliu88 almost 2 years ago - 5 comments

#26 - common trigger for array of write-buffered registers

Issue - State: closed - Opened by mkahane almost 2 years ago - 2 comments
Labels: question

#25 - Address with appears to max out at 24 bits

Issue - State: closed - Opened by asicguy almost 2 years ago - 2 comments
Labels: feature request

#24 - Plans To Generate Decoder For Multiple Register Blocks

Issue - State: closed - Opened by mkahane almost 2 years ago - 2 comments

GitHub / SystemRDL/PeakRDL-regblock issues and pull requests