Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / SpinalHDL/SpinalHDL issues and pull requests

#1549 - VexiiRiscv related dev PR

Pull Request - State: open - Opened by Dolu1990 5 days ago

#1548 - [regif] chead define macro format update

Pull Request - State: closed - Opened by jijingg 5 days ago

#1547 - Fix the issue that negative BigDecimal can not be assigned to AFix

Pull Request - State: closed - Opened by JunyiLiu1994 5 days ago - 1 comment

#1544 - Fix some issues in WidthAdapter of TileLink

Pull Request - State: closed - Opened by JunyiLiu1994 9 days ago - 1 comment

#1543 - StreamCCByToggle Altera attributes

Pull Request - State: closed - Opened by g0t00 12 days ago - 11 comments

#1542 - StreamFork2.takes has a small mistake

Issue - State: closed - Opened by ramielkhatibPQS 12 days ago - 1 comment

#1541 - Fix negation for AFix

Pull Request - State: closed - Opened by JunyiLiu1994 13 days ago - 1 comment

#1539 - Fix unconnected port comma issue

Pull Request - State: closed - Opened by g0t00 14 days ago - 1 comment

#1538 - Fix the wrong directory when generating .lst of Verilog/SV

Pull Request - State: open - Opened by Tikifire 14 days ago

#1537 - Unconnected IO Port generates incorrect verilog

Issue - State: closed - Opened by g0t00 15 days ago

#1534 - `PackedBundle` inside `Union`?

Issue - State: open - Opened by KireinaHoro 20 days ago - 5 comments

#1533 - Implement DDRx Controller by Bmb2Dfi

Pull Request - State: open - Opened by liyaohou 21 days ago

#1531 - Vivado/Vitis post simulation

Issue - State: open - Opened by yao-baijian 22 days ago - 3 comments

#1529 - Fix FSM bug

Pull Request - State: open - Opened by thajohns 23 days ago - 4 comments

#1527 - duplicate module when multi inst

Issue - State: closed - Opened by hy0000 24 days ago

#1526 - Set Name for asyncAssertSyncDeassert

Pull Request - State: closed - Opened by g0t00 25 days ago - 1 comment

#1525 - Misc docs

Pull Request - State: closed - Opened by thajohns 25 days ago - 1 comment

#1523 - regif's html doc not support setname function

Issue - State: open - Opened by laodao01 26 days ago

#1522 - printFilelist Option and regif SVHeader format fix

Pull Request - State: closed - Opened by jijingg 26 days ago

#1520 - Mill project file updated.

Pull Request - State: closed - Opened by Readon 30 days ago - 9 comments

#1519 - fetch resource independently to avoid a fail while missing one type o…

Pull Request - State: closed - Opened by Readon about 1 month ago - 1 comment

#1518 - fix mill support cross platform.

Pull Request - State: closed - Opened by Readon about 1 month ago - 4 comments

#1517 - Omit toplevel in component path for naming

Pull Request - State: closed - Opened by KireinaHoro about 1 month ago - 1 comment

#1516 - Fix regression from #1506: allow mill to locate version config file

Pull Request - State: closed - Opened by KireinaHoro about 1 month ago - 1 comment

#1515 - Fix infinite loop on zero-length read for `Axi4Master`

Pull Request - State: closed - Opened by KireinaHoro about 1 month ago - 1 comment

#1514 - synchronous StreamFork valid/ready are not decoupled properly

Issue - State: closed - Opened by ramielkhatibPQS about 1 month ago - 3 comments

#1513 - Add support for AMBA5 CHI？

Issue - State: open - Opened by tanhongze about 1 month ago - 1 comment

#1512 - Inconsistent naming for nested `Composite` areas

Issue - State: closed - Opened by KireinaHoro about 1 month ago - 2 comments

#1511 - Memory of Depth 1 Produces Unhelpful Error Message

Issue - State: closed - Opened by knapheide about 1 month ago - 1 comment

#1510 - Assign bits (BigInt) back to Bundle/Union/Enum in SpinalSim

Issue - State: open - Opened by KireinaHoro about 1 month ago - 8 comments

#1508 - LATCH DETECTED from the combinatorial signal

Issue - State: closed - Opened by Sanchit-Gupta10 about 1 month ago - 3 comments

#1506 - Mill support on windows

Pull Request - State: closed - Opened by Readon about 1 month ago - 4 comments

#1505 - Add mill template link to readme

Pull Request - State: open - Opened by mrcmry about 2 months ago - 2 comments

#1503 - Problems with `setCompositeName` in combination with `removePruned`

Issue - State: closed - Opened by knapheide about 2 months ago - 1 comment

#1502 - correct misspelling for issue: defualtReadBits spelling mistake #1494

Pull Request - State: closed - Opened by laodao01 about 2 months ago - 1 comment

#1501 - XSIM backend not working on Linux

Issue - State: open - Opened by ramielkhatibPQS about 2 months ago

#1500 - Add SamplerCC pushCd(reg) -> popCd(BufferCC)

Pull Request - State: open - Opened by Dolu1990 about 2 months ago

#1499 - switch SInt support

Issue - State: open - Opened by DoubiZhizun about 2 months ago

#1498 - switch SInt support

Issue - State: closed - Opened by DoubiZhizun about 2 months ago

#1497 - SystemVerilog Generation

Issue - State: open - Opened by digee-bytes 2 months ago

#1496 - no waveforms displayed when using xsim

Issue - State: closed - Opened by shjdgwj 2 months ago - 5 comments

#1495 - Allow randomizing TKEEP/TSTRB for Axi4StreamMaster

Pull Request - State: closed - Opened by KireinaHoro 2 months ago - 1 comment

#1494 - defualtReadBits spelling mistake

Issue - State: closed - Opened by laodao01 2 months ago - 1 comment

#1493 - Fix timescale of the trace files generated by the Verilator backend

Pull Request - State: closed - Opened by RolinBert 2 months ago - 1 comment

#1491 - fix incorrect right-shift of signed AFix

Pull Request - State: closed - Opened by thajohns 2 months ago - 1 comment

#1490 - signed `AFix` right shift does not sign-extend

Issue - State: closed - Opened by thajohns 2 months ago

#1489 - Regif bugfix

Pull Request - State: closed - Opened by jijingg 2 months ago

#1488 - Allow bypass of Payload in same stage as insert.

Issue - State: closed - Opened by NikLeberg 2 months ago - 2 comments

#1487 - Fix SpinalSim segfault on Verilator 5.026

Pull Request - State: closed - Opened by KireinaHoro 2 months ago - 1 comment

#1485 - Add `caseRom` option

Pull Request - State: closed - Opened by bunnie 2 months ago - 1 comment

#1484 - set rst name for default clock domain by ClockDomainConfig

Pull Request - State: open - Opened by yportne13 3 months ago - 1 comment

#1481 - file miss

Issue - State: open - Opened by ICJJ 3 months ago - 2 comments

#1480 - Fix #1477 : AFix.* remove unecessary resize

Pull Request - State: closed - Opened by Dolu1990 3 months ago

#1477 - Unnecessary resizing of multiplicands when multiplying `AFix`es

Issue - State: closed - Opened by thajohns 3 months ago - 2 comments

#1476 - Observations about AFix

Issue - State: open - Opened by thajohns 3 months ago - 3 comments

#1475 - RFC: Add blackboxing for simple 1-port synchronous ROMs

Pull Request - State: open - Opened by bunnie 3 months ago - 16 comments

#1473 - freeze state

Issue - State: closed - Opened by ICJJ 3 months ago - 7 comments

#1472 - add newline to VpiBackend output

Pull Request - State: closed - Opened by Nik-Sch 3 months ago - 1 comment

#1471 - type support

Issue - State: closed - Opened by ztachip 3 months ago - 1 comment

#1470 - sonatype release process is broken

Issue - State: closed - Opened by Dolu1990 3 months ago - 5 comments

#1469 - Possible pull request: PipelinedMemoryBusToApbBridge for APB4

Issue - State: open - Opened by juliaazziz 3 months ago - 1 comment

#1468 - validate component and declaration naming

Pull Request - State: closed - Opened by NikLeberg 3 months ago - 5 comments

#1467 - testbench of USB device

Issue - State: open - Opened by Mina-Lrh 3 months ago - 6 comments

#1466 - Fix attempt to #1465

Pull Request - State: closed - Opened by Dolu1990 3 months ago

#1465 - `:=` behaves unexpectedly on `Fragment[BaseType]`

Issue - State: closed - Opened by knapheide 3 months ago

#1464 - How about ignore the clone error while using generate in insert of Node.

Issue - State: closed - Opened by Readon 3 months ago - 1 comment

#1463 - formal: GlobalClock() produces invalid VHDL

Issue - State: open - Opened by NikLeberg 3 months ago - 6 comments

#1462 - Attributes on IO result in invalid syntax in VHDL

Issue - State: closed - Opened by NikLeberg 3 months ago - 4 comments

#1461 - Issues with newer Verilator Versions

Issue - State: closed - Opened by saahm 3 months ago - 1 comment

#1460 - Added skipOver method to PackedBundle

Pull Request - State: closed - Opened by dokleina 3 months ago - 1 comment

#1459 - Payloads cross StageLink would be elborated into combinational logic.

Issue - State: closed - Opened by Readon 3 months ago - 1 comment

#1457 - Packed bundle assignment bug

Pull Request - State: closed - Opened by dokleina 4 months ago - 3 comments

#1456 - add driveTo method return stream directly.

Pull Request - State: closed - Opened by Readon 4 months ago - 2 comments

#1455 - Use latest docker release for CI.

Pull Request - State: closed - Opened by Readon 4 months ago

#1454 - Fix for yosys0.41

Pull Request - State: closed - Opened by Readon 4 months ago

#1453 - add translateBy function which return the new Stream.

Pull Request - State: closed - Opened by Readon 4 months ago - 2 comments

#1452 - add secure error for write and read

Pull Request - State: closed - Opened by jijingg 4 months ago

#1451 - switch generate redundant verilog code

Issue - State: closed - Opened by cb38 4 months ago - 3 comments

#1451 - switch generate redundant verilog code

Issue - State: closed - Opened by cb38 4 months ago - 3 comments

#1450 - ACE & ACE-Lite support

Pull Request - State: open - Opened by KireinaHoro 4 months ago - 1 comment

#1450 - ACE & ACE-Lite support

Pull Request - State: open - Opened by KireinaHoro 4 months ago - 1 comment

#1448 - Constraint writer: use regex to match for net names

Pull Request - State: open - Opened by KireinaHoro 4 months ago

#1448 - Constraint writer: use regex to match for net names

Pull Request - State: closed - Opened by KireinaHoro 4 months ago - 1 comment

#1447 - [regif] Ram addr width issue fix

Pull Request - State: closed - Opened by jijingg 4 months ago

#1447 - [regif] Ram addr width issue fix

Pull Request - State: closed - Opened by jijingg 4 months ago

#1446 - About convenient anonymous bundle.

Issue - State: closed - Opened by Readon 4 months ago - 6 comments