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GitHub / PyHDI/Pyverilog issues and pull requests

#136 - Fix declassign regs

Pull Request - State: open - Opened by Jiahui17 4 months ago

#132 - fix: :bug: merge pr and fix struct statement

Pull Request - State: closed - Opened by Crescentm 9 months ago - 1 comment

#130 - fix: parsing of ansi style localparam declarations

Pull Request - State: open - Opened by mclark-iontra about 1 year ago

#129 - ANSI Style localparam causes parsing error

Issue - State: open - Opened by mclark-iontra about 1 year ago

#128 - Codegen arrays

Issue - State: open - Opened by CapucinedeBoissac over 1 year ago

#127 - Unsized numbers without base solution

Issue - State: open - Opened by YSJL over 1 year ago

#126 - parser error

Issue - State: open - Opened by 1353369570 almost 2 years ago

#125 - Attribute error in parser

Issue - State: open - Opened by KatCe almost 2 years ago

#124 - Parse Error: Cannot parse a function

Issue - State: open - Opened by KatCe almost 2 years ago - 1 comment

#123 - Preprocessing Issue when included file is in different directory

Issue - State: closed - Opened by YSJL almost 2 years ago - 1 comment

#122 - AST node

Issue - State: open - Opened by lijiale6224 almost 2 years ago - 1 comment

#121 - Can not support "generate case" statement

Issue - State: open - Opened by TonyLiaoZP about 2 years ago

#120 - fix: unexpected keyword argument `reorder`

Pull Request - State: open - Opened by superpung about 2 years ago - 4 comments

#119 - Added support for automatic functions

Pull Request - State: open - Opened by Lucaz97 over 2 years ago - 1 comment

#118 - unsufficient parse for large scale verilog design

Issue - State: open - Opened by ZhaoYunfei123 over 2 years ago

#117 - TypeError: generate() got an unexpected keyword argument 'reorder'

Issue - State: open - Opened by Sanjaya97 over 2 years ago - 3 comments

#116 - Unsized numbers without base not supported

Issue - State: open - Opened by Louis-DR over 2 years ago - 2 comments

#115 - Specify statements

Issue - State: open - Opened by lilasrahis over 2 years ago - 1 comment

#114 - Parsing Issues

Issue - State: open - Opened by kwmartin almost 3 years ago - 1 comment

#113 - ParseError for User Defined Primitives

Issue - State: open - Opened by TheMatt2 almost 3 years ago - 1 comment
Labels: wontfix

#112 - Parser Error for resettable D Flip-Flop

Issue - State: open - Opened by kwmartin almost 3 years ago - 1 comment

#111 - Parse Error for Inverter Gate

Issue - State: open - Opened by kwmartin almost 3 years ago

#110 - Parsing Error for integer memories

Issue - State: open - Opened by kwmartin almost 3 years ago

#109 - dataflow analysis error

Issue - State: open - Opened by cemery123 almost 3 years ago - 5 comments

#108 - Extracting design information via API

Issue - State: open - Opened by svenka3 almost 3 years ago

#107 - Defparam support

Pull Request - State: closed - Opened by trharoldsen about 3 years ago

#106 - How to setup and install pyverilog inside py virtual environment?

Issue - State: closed - Opened by usman1515 about 3 years ago - 1 comment

#105 - About control flow analysis

Issue - State: open - Opened by earphonebreaker about 3 years ago

#104 - windows error -run example_parser.py

Issue - State: closed - Opened by TobyLQ about 3 years ago - 1 comment

#103 - Support SVA assert/assume

Pull Request - State: open - Opened by zhanghongce about 3 years ago - 1 comment

#102 - A bug when parsing nesting ifStatement

Issue - State: open - Opened by Yang-Qirui over 3 years ago

#101 - [wip] Add support for functions declarations with port list

Pull Request - State: open - Opened by noloerino over 3 years ago - 1 comment

#100 - Functions with port lists can't be parsed

Issue - State: open - Opened by noloerino over 3 years ago

#99 - Use context manager to avoid ResourceWarning

Pull Request - State: closed - Opened by leonardt over 3 years ago

#98 - [PARTSELECT PLUS MINUS FIX] Fixed the MSB or LSB computation for the …

Pull Request - State: open - Opened by loopyK1ng over 3 years ago - 3 comments

#97 - TypeError: generate() got an unexpected keyword argument 'reorder'

Issue - State: open - Opened by venkateshknpl almost 4 years ago - 2 comments

#96 - error

Issue - State: open - Opened by 61cc almost 4 years ago

#95 - Modify AST generated by PyVerilog

Issue - State: open - Opened by sazadur about 4 years ago

#94 - How to append new assign to a module from verilog code?

Issue - State: open - Opened by zilongwang123 about 4 years ago

#93 - how

Issue - State: open - Opened by zilongwang123 about 4 years ago

#92 - Error running example_graphgen.py

Issue - State: open - Opened by zhileiren about 4 years ago - 1 comment

#91 - gate level netlist to rtl

Issue - State: open - Opened by very3b about 4 years ago

#90 - isWireArray(termtype) is missing in /utils/signaltype.py

Issue - State: open - Opened by teaalltr over 4 years ago - 3 comments

#89 - OSError: Format: "dot" not recognized. Use one of:

Issue - State: open - Opened by faruqui13 over 4 years ago

#88 - Added end_lineno to indicate the last line number in always, module, …

Pull Request - State: closed - Opened by dyadav7 over 4 years ago - 1 comment

#87 - SVA assert / assume/ cover property support

Issue - State: open - Opened by dyadav7 over 4 years ago - 1 comment
Labels: enhancement

#86 - question regarding implementation

Issue - State: closed - Opened by nancychang42 over 4 years ago - 1 comment

#85 - Not able to run

Issue - State: open - Opened by KaranThakur1998 over 4 years ago

#84 - ast.IntConst creates collisions on dicts

Issue - State: open - Opened by Lucaz97 over 4 years ago - 2 comments

#83 - vparser/parser.py mkdir arguement error

Issue - State: closed - Opened by GrantBrown1994 over 4 years ago - 1 comment

#82 - Delays incorrectly printed on output to verilog

Issue - State: open - Opened by jandreasen3 over 4 years ago - 1 comment
Labels: bug

#81 - Can it work on hierarchy of design?

Issue - State: open - Opened by jadonrahul over 4 years ago - 2 comments

#80 - The verilog parser doesn't support the dot operator in the module header

Issue - State: open - Opened by Manarabdelaty over 4 years ago - 1 comment

#78 - Module Initiation Syntax

Issue - State: closed - Opened by HamzaShabbir517 over 4 years ago

#77 - function in module can not be parse, and get error

Issue - State: open - Opened by asky26 over 4 years ago - 13 comments
Labels: question

#76 - Assignment with strength does not compile

Issue - State: open - Opened by vperrin59 over 4 years ago
Labels: enhancement, question

#75 - Sample code for feature extraction from verlog file

Issue - State: open - Opened by SutirthaChakraborty over 4 years ago
Labels: question

#74 - New release with latest ply

Issue - State: closed - Opened by Blaok over 4 years ago - 3 comments

#73 - File not found error

Issue - State: open - Opened by rkaydivergent over 4 years ago
Labels: question

#71 - Question: replace parameter with its value

Issue - State: closed - Opened by jxxp9 over 4 years ago - 2 comments

#69 - could i auto-generate verilog code from a AST.

Issue - State: closed - Opened by jiahanwen95 over 4 years ago - 1 comment

#68 - Why does p_taskvardecl not support Output types?

Issue - State: closed - Opened by sjalloq almost 5 years ago - 1 comment

#67 - Howto analysis verilog basing on filelist

Issue - State: closed - Opened by joeji521 almost 5 years ago - 1 comment

#66 - Task call parsing failure

Issue - State: open - Opened by VibhorDodeja almost 5 years ago - 1 comment
Labels: enhancement

#65 - how to output the AST from verilog?

Issue - State: closed - Opened by lixun1997 almost 5 years ago - 1 comment

#64 - Feature addition: Verilog code in Python strings along with verilog files.

Pull Request - State: closed - Opened by ndyashas almost 5 years ago - 2 comments

#63 - Code strings option in addition to input file list

Issue - State: closed - Opened by ndyashas almost 5 years ago - 2 comments

#61 - SV parse error

Issue - State: open - Opened by sjalloq about 5 years ago - 2 comments
Labels: enhancement

#60 - Parser error when no newline at end of file

Issue - State: open - Opened by sjalloq about 5 years ago - 1 comment
Labels: bug

#59 - AST node start position and end position support

Issue - State: open - Opened by jinfuchen about 5 years ago - 2 comments
Labels: enhancement, question

#58 - How to debug a yacc parse error?

Issue - State: open - Opened by sjalloq about 5 years ago - 3 comments
Labels: question

#57 - Adding basic support for CASEZ statements

Pull Request - State: closed - Opened by ghost over 5 years ago

#56 - test error

Issue - State: open - Opened by sheriefreda over 5 years ago - 2 comments

#55 - add parsing rule, function integer ID

Pull Request - State: closed - Opened by JaewonHur over 5 years ago

#54 - Req1. add parsing rule, integer declaration and initialization.

Pull Request - State: closed - Opened by JaewonHur over 5 years ago

#53 - Windows operation

Issue - State: open - Opened by kessel055 over 5 years ago - 1 comment

#52 - how to generate case

Issue - State: closed - Opened by Raymondwo over 5 years ago - 1 comment

#51 - Extend parser for n-d array support

Pull Request - State: closed - Opened by rsetaluri almost 6 years ago - 1 comment

#50 - Added a number of configuration options

Pull Request - State: closed - Opened by donn almost 6 years ago

#48 - add-inout

Pull Request - State: closed - Opened by tomchean about 6 years ago

#47 - add preliminary support for `always_latch`

Pull Request - State: closed - Opened by hofstee about 6 years ago

#46 - verilog to ast

Issue - State: open - Opened by yom1994 about 6 years ago - 1 comment

#45 - Add comma separated edgesigs

Pull Request - State: closed - Opened by hofstee about 6 years ago

#44 - Enhancement: Support for "automatic"

Issue - State: open - Opened by shtaxxx over 6 years ago

#43 - PyVerilog does not handle genvar and generate blocks

Issue - State: open - Opened by anandh1791 over 6 years ago - 4 comments

#42 - New Tokens in PyVerilog

Issue - State: closed - Opened by monibahmed over 6 years ago - 2 comments

#41 - A small syntax bug in ast.py line 28, within show function

Issue - State: closed - Opened by tanhongze over 6 years ago - 1 comment

#40 - Add end lineno

Pull Request - State: closed - Opened by rsetaluri over 6 years ago

#39 - "parameter real" is not supported

Issue - State: open - Opened by sbourdeauducq over 6 years ago - 2 comments

#38 - Preliminary support for SystemVerilog logic, always_ff, always_comb, unique case

Pull Request - State: closed - Opened by leonardt almost 7 years ago - 3 comments

#37 - It fails to parse two-dimensional array

Issue - State: open - Opened by chsiensu almost 7 years ago - 3 comments