Ecosyste.ms: Issues

An open API service for providing issue and pull request metadata for open source projects.

GitHub / Nic30/hwt issues and pull requests

#46 - Incorrect initialization with Verilog serializer

Issue - State: open - Opened by jesseclin 11 months ago - 3 comments

#45 - Native Async reset support in RtlNetlist?

Issue - State: open - Opened by jesseclin 11 months ago - 4 comments

#44 - Update signalOps.py

Pull Request - State: closed - Opened by jesseclin 12 months ago - 1 comment

#43 - Instantiate VHDL or Verilog IPs as black-boxes

Issue - State: open - Opened by jesseclin 12 months ago - 2 comments

#42 - assigment semantics unclear

Issue - State: closed - Opened by philipaxer about 2 years ago - 2 comments

#41 - add_param_asserts breaks examples

Issue - State: closed - Opened by philipaxer about 2 years ago - 5 comments

#40 - Issues with basic example

Issue - State: closed - Opened by kiteloopdesign over 3 years ago - 3 comments

#39 - Complete tests for assignments to a cast or slice of registers

Issue - State: closed - Opened by Nic30 about 4 years ago - 1 comment

#38 - Tests for StructIntf._eq/__ne__ operators

Issue - State: closed - Opened by Nic30 about 4 years ago - 1 comment

#37 - Tests for replace_input_in_expr

Issue - State: closed - Opened by Nic30 about 4 years ago - 1 comment

#36 - Complete tests for RtlSignals generated from composed types like HStruct, HArray

Issue - State: closed - Opened by Nic30 about 4 years ago - 1 comment

#35 - Add a Gitter chat badge to README.md

Pull Request - State: closed - Opened by gitter-badger over 4 years ago

#34 - IP core importing

Issue - State: open - Opened by Nic30 almost 5 years ago - 3 comments
Labels: enhancement

#33 - Support for formal verification statements

Issue - State: closed - Opened by Nic30 about 5 years ago - 2 comments

#32 - Convert interfaces to HDL as well (VHDL records, SV interface)

Issue - State: open - Opened by Nic30 about 5 years ago
Labels: enhancement

#31 - Multiple component variants for specified parameter combinations under wrapper

Issue - State: closed - Opened by Nic30 about 5 years ago - 2 comments
Labels: enhancement

#30 - rm relicts of interface direction discoverry logic

Issue - State: closed - Opened by Nic30 about 5 years ago - 1 comment

#29 - Proper tutorial - python project packaging and distribution, doc, visualization

Issue - State: open - Opened by Nic30 about 5 years ago - 1 comment

#28 - Prevent from dupliacation of generic/params if it shares same value

Issue - State: closed - Opened by Nic30 about 5 years ago - 1 comment

#27 - Proper tutorial - simulations/verifications

Issue - State: open - Opened by Nic30 about 5 years ago - 2 comments

#25 - Proper tutorial - components, interfaces

Issue - State: open - Opened by Nic30 about 5 years ago - 2 comments

#24 - CLI utils for component/interface introspectivity

Issue - State: closed - Opened by Nic30 about 5 years ago - 1 comment

#23 - Clean stack trace for exception in RtlSignal operators

Issue - State: closed - Opened by Nic30 about 5 years ago - 1 comment

#22 - multidimensional index in vhdl

Issue - State: closed - Opened by Nic30 over 5 years ago - 1 comment

#21 - Error with sensitivity lists in If statement

Issue - State: closed - Opened by benreynwar over 5 years ago - 2 comments

#20 - Extract rtl simulator

Issue - State: closed - Opened by Nic30 over 5 years ago - 1 comment

#19 - Extract bit precise math

Issue - State: closed - Opened by Nic30 over 5 years ago - 1 comment

#18 - replace internal representation of hardware with netlistDB

Issue - State: closed - Opened by Nic30 almost 6 years ago - 1 comment

#17 - naming optimizations

Issue - State: open - Opened by Nic30 about 6 years ago

#16 - Extraction of netlist graph database and HDL parser/serializer modules

Issue - State: closed - Opened by Nic30 about 6 years ago - 4 comments

#15 - Extract the simulator

Issue - State: closed - Opened by Nic30 about 6 years ago - 2 comments

#14 - minor review of README

Pull Request - State: closed - Opened by mgielda about 6 years ago - 2 comments

#13 - Help with design low-level HDL language

Issue - State: closed - Opened by XVilka over 6 years ago - 3 comments

#12 - Interface direction in definition of component

Issue - State: closed - Opened by Nic30 over 6 years ago - 1 comment

#11 - C/C++ library for IO access to HW in sim. (for driver development)

Issue - State: closed - Opened by Nic30 over 6 years ago - 4 comments

#10 - Extract interface arrays

Issue - State: closed - Opened by Nic30 over 6 years ago - 1 comment

#9 - readable debug of Value instances

Issue - State: closed - Opened by Nic30 almost 7 years ago - 2 comments

#8 - Condition tree rework

Issue - State: closed - Opened by Nic30 about 7 years ago - 1 comment
Labels: enhancement

#7 - Quartus ip core compatibility

Issue - State: closed - Opened by Nic30 about 7 years ago - 3 comments
Labels: enhancement

#6 - tests for operators with signed Bits

Issue - State: closed - Opened by Nic30 over 7 years ago - 1 comment

#5 - Add a Gitter chat badge to README.md

Pull Request - State: closed - Opened by gitter-badger about 8 years ago

#4 - If then else block can't find its block automaticaly

Issue - State: closed - Opened by Nic30 about 9 years ago - 1 comment

#3 - Params are not working at hierarchical interfaces

Issue - State: closed - Opened by Nic30 about 9 years ago - 1 comment

#2 - params are not set on component instances

Issue - State: closed - Opened by Nic30 about 9 years ago - 1 comment

#1 - Value of param at top level is invalid

Issue - State: closed - Opened by Nic30 about 9 years ago