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GitHub / Nic30/hdlConvertorAst issues and pull requests

#8 - How HDLConvertorAst support SystemVerilog

Issue - State: closed - Opened by fzwwj95 almost 2 years ago - 1 comment

#7 - Verilog or System Verilog：How could I get the pure Verilog code without System Verilog syntax?

Issue - State: open - Opened by Hovennnnn almost 2 years ago - 1 comment

#6 - SystemVerilog: multiple packed dimensions not processed correctly

Issue - State: open - Opened by theo-scott over 3 years ago - 2 comments

#5 - HdlStmIf: cond, if_true property useless

Issue - State: open - Opened by Nic30 about 4 years ago

#4 - Adding support for VHDL physical types

Pull Request - State: closed - Opened by mewais about 4 years ago - 1 comment

#3 - localparam with operator **

Issue - State: closed - Opened by dramoz over 4 years ago - 2 comments

#2 - PackageParser.visitConstant_declaration Conversion to Python object not implemented

Issue - State: closed - Opened by mewais over 4 years ago - 8 comments

#1 - Error when call visit_HdlContext NotImplementedError: Unexpected object of type

Issue - State: closed - Opened by jinfuchen over 4 years ago - 5 comments