Ecosyste.ms: Issues
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GitHub / David-Durst/frail issues and pull requests
#19 - Adds strength reduction and minimal nested counter rewrite rules
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#18 - Verilog fixes for counter; 2 loop affine counter example test passes
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#17 - Adds "functional model" frail code for affine + piecewise affine
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#16 - Revert "remove lake dependency from frail so frail can be used in lake instead"
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#15 - remove lake dependency from frail so frail can be used in lake instead
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#14 - Changes to support lake integration
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#13 - add optional step input to go to next address
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#12 - make default 16, not 32 bits
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#11 - Updates designs such that current Verilog tests pass
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#10 - Using A Single Forall At End Of All Time Steps
Pull Request -
State: closed - Opened by David-Durst over 3 years ago
#9 - Better fixes for repeated signals in Verilog issues
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
- 4 comments
#8 - Verilog fixes
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#7 - add lake package to setup
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#6 - added tests for design_a with model, fixed bug with first addr timing
Pull Request -
State: closed - Opened by kavyasreedhar over 3 years ago
#5 - First Iteration Of Verilog Generation
Pull Request -
State: closed - Opened by David-Durst almost 4 years ago
#4 - inline recurrenceseq as well
Pull Request -
State: closed - Opened by kavyasreedhar almost 4 years ago
#3 - Rebase nicer print (rebased on SMT stuff)
Pull Request -
State: closed - Opened by David-Durst almost 4 years ago
#2 - Generated SMT Code Runs But Is Slow
Pull Request -
State: closed - Opened by David-Durst almost 4 years ago
#1 - Nicer debug printing
Pull Request -
State: closed - Opened by kavyasreedhar almost 4 years ago
- 1 comment