Ecosyste.ms: Issues

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GitHub / David-Durst/aetherling issues and pull requests

#31 - Bump pygments from 2.2.0 to 2.7.4

Pull Request - State: open - Opened by dependabot[bot] over 3 years ago
Labels: dependencies

#30 - Bump jinja2 from 2.10.1 to 2.11.3

Pull Request - State: open - Opened by dependabot[bot] over 3 years ago
Labels: dependencies

#29 - Bump pillow from 6.2.0 to 8.1.1

Pull Request - State: open - Opened by dependabot[bot] over 3 years ago
Labels: dependencies

#28 - File Crash With Verilator/Clang

Issue - State: open - Opened by David-Durst over 4 years ago

#27 - Bump pillow from 6.0.0 to 6.2.0

Pull Request - State: closed - Opened by dependabot[bot] over 4 years ago - 1 comment
Labels: dependencies

#26 - Map Is Slow

Issue - State: closed - Opened by David-Durst over 4 years ago - 3 comments

#25 - 1D Stencil Is Very Slow

Issue - State: open - Opened by David-Durst over 4 years ago - 6 comments

#24 - CoreIR Won't Compile Circuit That Simulates Correctly

Issue - State: open - Opened by David-Durst almost 5 years ago

#23 - Can't Access ROM From CoreIR Through Magma

Issue - State: open - Opened by David-Durst almost 5 years ago - 2 comments

#22 - CoreIR URem Not Being Generator For Verilator

Issue - State: closed - Opened by David-Durst almost 5 years ago - 1 comment

#21 - Verilator Rather Than CoreIR Catching Unconnected Wires

Issue - State: closed - Opened by David-Durst almost 5 years ago - 2 comments

#20 - CoreIR Undefined Symbol On Travis

Issue - State: closed - Opened by David-Durst almost 5 years ago - 1 comment

#19 - Possible Aetherling/CoreIR Memory Leak

Issue - State: open - Opened by David-Durst about 5 years ago - 1 comment

#18 - Port Renamed Incorrectly

Issue - State: closed - Opened by David-Durst about 5 years ago

#17 - Linebuffer RAM Not Being Written To When CE On

Issue - State: closed - Opened by David-Durst over 5 years ago - 4 comments

#16 - Finished my work on reduce partially parallel

Pull Request - State: closed - Opened by David-Durst almost 6 years ago

#15 - Put 1D and 2D Linebuffer into Master

Pull Request - State: closed - Opened by David-Durst almost 6 years ago

#14 - Add 1D and 2D Linebuffers

Pull Request - State: closed - Opened by David-Durst almost 6 years ago

#13 - Adding ReducePartiallyParallel

Pull Request - State: closed - Opened by adamdai almost 6 years ago

#12 - Native Linebuffer Fails With _Mux2 Name Issue

Issue - State: closed - Opened by David-Durst almost 6 years ago - 3 comments

#11 - Dashes in generated verilog names

Issue - State: closed - Opened by adamdai almost 6 years ago - 1 comment

#10 - CoreIR Core Dumps Only In Travis

Issue - State: closed - Opened by David-Durst almost 6 years ago - 1 comment

#9 - changed setup.py to accomodate newer version of pip

Pull Request - State: closed - Opened by adamdai almost 6 years ago

#8 - Simulator update and Array Repack/Reshape redesign

Pull Request - State: closed - Opened by akeley98 almost 6 years ago

#7 - Adding ND Linebuffer

Pull Request - State: closed - Opened by David-Durst about 6 years ago

#6 - Fixing the forgotten n

Pull Request - State: closed - Opened by David-Durst about 6 years ago

#5 - fixing show for ratios

Pull Request - State: closed - Opened by David-Durst about 6 years ago

#4 - Can't Make a Linebuffer at 2 px per clock for 3 px window

Issue - State: closed - Opened by David-Durst about 6 years ago - 1 comment

#3 - Port Direction Issue

Issue - State: open - Opened by David-Durst about 6 years ago - 9 comments

#2 - Shift_x Wrong Type Signature Or Example

Issue - State: closed - Opened by David-Durst over 6 years ago - 1 comment

#1 - Signature of Conv_x and Conv_t

Issue - State: closed - Opened by David-Durst over 6 years ago - 5 comments